SAM7S32 Atmel Corporation, SAM7S32 Datasheet - Page 105
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SAM7S32
Manufacturer Part Number
SAM7S32
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S32
Flash (kbytes)
32 Kbytes
Pin Count
48
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
21
Ext Interrupts
21
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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19. Embedded Flash Controller (EFC)
19.1
19.2
19.2.1
Table 19-1.
6175L–ATARM–28-Jul-11
SAM7S512
32
2
Overview
Functional Description
Embedded Flash Organization
SAM7S256
Product Specific Lock and General-purpose NVM Bits
16
2
The Embedded Flash Controller (EFC ) is a part of the Memory Controller and ensures the inter-
face of the Flash block with the 32-bit internal bus. It increases performance in Thumb Mode for
Code Fetch with its system of 32-bit buffers. It also manages the programming, erasing, locking
and unlocking sequences using a full set of commands.
The SAM7S512 is equipped with two EFCs, EFC0 and EFC1. EFC1 does not feature the Secu-
rity bit and GPNVM bit. The Security and GPNVM bits embedded only on EFC0 apply to the two
blocks in the SAM7S512.
The Embedded Flash interfaces directly to the 32-bit internal bus. It is composed of several
interfaces:
The Embedded Flash size, the page size and the lock region organization are described in the
product definition section.
SAM7S128
• One memory plane organized in several pages of the same size
• Two 32-bit read buffers used for code read optimization (see
• One write buffer that manages page programming. The write buffer size is equal to the page
• Several lock bits used to protect write and erase operations on lock regions. A lock region is
• Several general-purpose NVM bits. Each bit controls a specific feature in the device. Refer to
107).
size. This buffer is write-only and accessible all along the 1 MByte address space, so that
each word can be written to its final address (see
composed of several consecutive pages, and each lock region has its associated lock bit.
the product definition section to get the GPNVM assignment.
2
8
SAM7S64
16
2
SAM7S321
2
8
SAM7S32
2
8
SAM7S161
“Write Operations” on page
2
8
SAM7S16
“Read Operations” on page
2
8
SAM7S Series
Number of GPNVM bits
Number of Lock Bits
Denomination
109).
105
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