SAM7S32 Atmel Corporation, SAM7S32 Datasheet - Page 321
SAM7S32
Manufacturer Part Number
SAM7S32
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S32
Flash (kbytes)
32 Kbytes
Pin Count
48
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
21
Ext Interrupts
21
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Figure 30-10. Master Read with Multiple Data Bytes
30.7.6
30.7.6.1
6175L–ATARM–28-Jul-11
TXCOMP
RXRDY
TWD
Internal Address
S
7-bit Slave Addressing
Write START Bit
DADR
When a single data byte read is performed, with or without internal address (IADR), the START
and STOP bits must be set at the same time. See
performed, with or without internal address (IADR), the STOP bit must be set after the next-to-
last data received. See
Figure 30-9. Master Read with One Data Byte
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address
devices and 10-bit slave address devices.
When Addressing 7-bit slave devices, the internal address bytes are used to perform random
address (read or write) accesses to reach one or more data bytes, within a memory page loca-
tion in a serial memory, for example. When performing read operations with an internal address,
the TWI performs a write operation to set the internal address into the slave device, and then
switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is
sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See
Figure 30-11
The three internal address bytes are configurable through the Master Mode register
(TWI_MMR).
If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to
0.
R
A
and
TXCOMP
DATA n
RXRDY
Figure 30-13
TWD
Figure
Read RHR
A
S
DATA n
Write START &
30-10. For Internal Address usage see
for Master Write operation with internal address.
DATA (n+1)
STOP Bit
DADR
A
DATA (n+1)
Read RHR
R
DATA (n+m)-1
Figure
A
30-9. When a multiple data byte read is
DATA
DATA (n+m)-1
A
Read RHR
after next-to-last data read
DATA (n+m)
Read RHR
SAM7S Series
Write STOP Bit
Section
N
P
Figure
30.7.6.
N
30-12. See
DATA (n+m)
Read RHR
P
321
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