SAM7S161 Atmel Corporation, SAM7S161 Datasheet - Page 485

• Manufacturer Part Number: SAM7S161
• Manufacturer: Atmel Corporation

Specifications of SAM7S161

• Flash (kbytes): 16 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6175L–ATARM–28-Jul-11
Figure 34-6. Synchronized Period or Duty Cycle Update
To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to
synchronize his software. Two methods are possible. In both, the user must enable the dedi-
cated interrupt in PWM_IER at PWM Controller level.
The first method (polling method) consists of reading the relevant status bit in PWM_ISR Regis-
ter according to the enabled channel(s). See
The second method uses an Interrupt Service Routine associated with the PWM channel.
Note:
Figure 34-7. Polling Method
Note:
Reading the PWM_ISR register automatically clears CHIDx flags.
Polarity and alignment can be modified only when the channel is disabled.
End of Cycle
Acknowledgement and clear previous register state
The last write has been taken into account
PWM_CPRDx
Update of the Period or Duty Cycle
Writing in PWM_CUPDx
PWM_CUPDx Value
Writing in CPD field
PWM_ISR Read
1
User's Writing
CHIDx = 1
Figure
YES
PWM_CDTYx
0
34-7.
PWM_CMRx. CPD
SAM7S Series
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