SAM3N1B Atmel Corporation, SAM3N1B Datasheet - Page 396

• Manufacturer Part Number: SAM3N1B
• Manufacturer: Atmel Corporation

Specifications of SAM3N1B

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.5.13
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396
SAM3N
SAM3N
Write Protection Registers
To prevent any single software error that may corrupt PIO behavior, certain address spaces can
be write-protected by setting the WPEN bit in the
(PIO_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the PIO Write Pro-
tect Status Register (PIO_WPSR) is set and the field WPVSRC indicates in which register the
write access has been attempted.
The WPVS flag is reset by writing the PIO Write Protect Mode Register (PIO_WPMR) with the
appropriate access key, WPKEY.
The protected registers are:
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“PIO Enable Register” on page 401
“PIO Disable Register” on page 401
“PIO Output Enable Register” on page 402
“PIO Output Disable Register” on page 403
“PIO Input Filter Enable Register” on page 404
“PIO Input Filter Disable Register” on page 404
“PIO Multi-driver Enable Register” on page 409
“PIO Multi-driver Disable Register” on page 410
“PIO Pull Up Disable Register” on page 411
“PIO Pull Up Enable Register” on page 411
“PIO Peripheral ABCD Select Register 1” on page 413
“PIO Peripheral ABCD Select Register 2” on page 414
“PIO Output Write Enable Register” on page 419
“PIO Output Write Disable Register” on page 419
“PIO Pad Pull Down Disable Register” on page 417
“PIO Pad Pull Down Status Register” on page 418
“PIO Write Protect Mode Register”
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10