SAM3N1B Atmel Corporation, SAM3N1B Datasheet - Page 158

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SAM3N1B

Manufacturer Part Number
SAM3N1B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3N1B

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
10.20.7
10.20.7.1
10.20.7.2
10.20.7.3
158
31
23
15
31
23
15
31
23
15
7
7
7
SAM3N
Interrupt Priority Registers
IPRm
IPR4
IPR3
30
22
14
30
22
14
30
22
14
6
6
6
The IPR0-IPR8 registers provide a 4-bit priority field for each interrupt (See the “Peripheral Iden-
tifiers” section of the datasheet for more details). These registers are byte-accessible. See the
register summary in
fields, that map up to four elements in the CMSIS interrupt priority array IP[0] to IP[32], as shown:
29
21
13
29
21
13
29
21
13
5
5
5
Table 10-27 on page 151
28
20
12
28
20
12
28
20
12
4
4
4
IP[4m+3]
IP[4m+2]
IP[4m+1]
IP[4m]
IP[19]
IP[18]
IP[15]
IP[14]
IP[13]
IP[12]
27
19
11
27
19
11
27
19
11
3
3
3
for their attributes. Each register holds four priority
26
18
10
26
18
10
26
18
10
2
2
2
25
17
25
17
25
17
9
1
9
1
9
1
11011A–ATARM–04-Oct-10
24
16
24
16
24
16
8
0
8
0
8
0

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