M40800 Atmel Corporation, M40800 Datasheet - Page 204

• Manufacturer Part Number: M40800
• Manufacturer: Atmel Corporation

Specifications of M40800

• Flash (kbytes): 0 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 40 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: No

AC and DC Parameters
7-32
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
rgh
rm
rqh
rqs
rs
rstd
rstl
rwd
rwh
sdtd
shbsf
shbsr
sih
sis
tbe
tbz
tckf
tckr
tdbgd
tpfd
tpfh
tprd
tprh
RANGEOUT0, RANGEOUT1 hold time from MCLKf
Reset guaranteed nonrecognition time
DBGRQ guaranteed non-recognition time
DBGRQ set up time to MCLKr for guaranteed recognition
Reset setup time to MCLKr for guaranteed recognition
nRESETf to D[31:0], DBGACK, nCPI, nENOUT, nEXEC, nMREQ,
SEQ valid
nRESET LOW for guaranteed reset
MCLKr to nRW valid
nRW hold time from MCLKr
SDOUTBS to TDO valid
TCK to SHCLKBS, SHCLK2BS falling
TCK to SHCLKBS, SHCLK2BS rising
Synchronous nFIQ, nIRQ hold from MCLKf with ISYNC=1
Synchronous nFIQ, nIRQ setup to MCLKf, with ISYNC=1
Address and Data bus enable time from TBEr
Address and Data bus disable time from TBEf
TCK to TCK1, TCK2 falling
TCK to TCK1, TCK2 rising
TCK to DBGACK, DBGRQI changing
TCKf to TAP outputs
TAP outputs hold time from TCKf
TCKr to TAP outputs
TAP outputs hold time from TCKr
Parameter
Copyright © 1994-2001. All rights reserved.
Table 7-23 AC timing parameters used in this chapter (continued)
Parameter
Type
Minimum
Maximum
Minimum
Minimum
Minimum
Maximum
Minimum
Maximum
Minimum
Maximum
Maximum
Maximum
Minimum
Minimum
Maximum
Maximum
Maximum
Maximum
Maximum
Maximum
Minimum
Maximum
Minimum
ARM DDI 0029G
Figure
cross
reference
Figure 7-13
Figure 7-11
Figure 7-13
Figure 7-13
Figure 7-11
Figure 7-19
Figure 7-1
Figure 7-1
-
-
-
Figure 7-12
Figure 7-12
Figure 7-6
Figure 7-6
-
-
-
-
-
-
-
Figure 7-19