M40800 Atmel Corporation, M40800 Datasheet - Page 154

• Manufacturer Part Number: M40800
• Manufacturer: Atmel Corporation

Specifications of M40800

• Flash (kbytes): 0 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 40 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: No

Instruction Cycle Timings
6.7
6-12
Load register
The first cycle of a load register instruction performs the address calculation. During the
second cycle the data is fetched from memory and the base register modification is
performed, if required. During the third cycle the data is transferred to the destination
register, and external memory is unused. This third cycle can normally be merged with
the next prefetch cycle to form one memory N-cycle.
Either the base, or destination, or both, can be the PC, and the prefetch sequence is
changed if the PC is affected by the instruction.
The data fetch can abort, and in this case the destination modification is prevented. In
addition, if the processor is configured for early abort, the base register write-back is
also prevented.
The cycle timings are listed in Table 6-9 where:
•
•
•
c represents the current processor mode:
—
—
d=0 if the T bit has been specified in the instruction (such as LDRT) and d=c at
all other times
s represents the size of the data transfer shown by MAS[1:0] (see Table 6-10 on
page 6-13).
Copyright © 1994-2001. All rights reserved.
c=0 for User mode
c=1 for all other modes
ARM DDI 0029G