M40800 Atmel Corporation, M40800 Datasheet - Page 145
M40800
Manufacturer Part Number
M40800
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(21 pages)
3.M40800.pdf
(18 pages)
4.M40800.pdf
(153 pages)
Specifications of M40800
Flash (kbytes)
0 Kbytes
Pin Count
100
Max. Operating Frequency
40 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
No
Calibrated Rc Oscillator
No
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6.1
ARM DDI 0029G
About the instruction cycle timing tables
In the following tables:
•
•
•
•
•
•
nMREQ and SEQ, are pipelined up to one cycle ahead of the cycle to which they
apply. They are shown in the cycle in which they appear and indicate the next
cycle type.
The address, MAS[1:0], nRW, nOPC, nTRANS, and TBIT signals, that appear
up to half a cycle ahead, are shown in the cycle to which they apply. The address
is incremented to prefetch instructions in most cases. Because the instruction
width is four bytes in ARM state and two bytes in Thumb state, the increment
varies accordingly.
The letter L is used to indicate instruction length:
—
—
The letter i is used to indicate the width of the instruction fetch output by
MAS[1:0]:
—
—
Terms placed inside brackets represent the contents of an address.
The • symbol indicates zero or more cycles.
Copyright © 1994-2001. All rights reserved.
four bytes in ARM state
two bytes in Thumb state.
i=2 in ARM state represents word accesses
i=1 in Thumb state represents halfword accesses.
Instruction Cycle Timings
6-3
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