ATxmega16D4 Atmel Corporation, ATxmega16D4 Datasheet - Page 50
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ATxmega16D4
Manufacturer Part Number
ATxmega16D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16D4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega16D4-AU
Manufacturer:
Atmel
Quantity:
438
Part Number:
ATxmega16D4-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega16D4-MH
Manufacturer:
Atmel
Quantity:
1 605
Company:
Part Number:
ATxmega16D4-MHR
Manufacturer:
SANYO
Quantity:
50
Part Number:
ATxmega16D4-MHR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
5.8
5.8.1
8210B–AVR–04/10
Register Description
CHnMUX – Event Channel n Multiplexer Register
.
• Bit 7:0 - CHnMUX[7:0]: Channel Multiplexer
These bits select the event source according to
devices regardless of if the peripheral is present or not. Selecting event sources from peripher-
als that are not present will give the same result as when this register is zero. When this register
is zero no events are routed through. Manually generated events will override the CHnMUX and
be routed to the event channel even if this register is zero.
Table 5-3.
Bit
Read/Write
Initial Value
CHnMUX[7:4]
0000
0000
0000
0000
0000
0000
0000
0000
0001
0001
0001
0001
0001
0001
0010
0010
0010
0011
0100
0101
0101
0110
0110
R/W
CHnMUX[7:0] Bit Settings
7
0
CHnMUX[3:0]
X
X
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
0
1
0
1
0
1
X
X
X
X
0
0
0
1
0
0
0
1
0
0
0
0
1
0
1
R/W
6
0
X
X
X
X
X
X
X
0
0
1
0
0
1
0
0
1
1
n
n
n
n
n
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
R/W
5
0
Group Configuration
RTC_OVF
RTC_CMP
ACA_CH0
ACA_CH1
ACA_WIN
ADCA_CHn
PORTA_PINn
PORTB_PINn
PORTC_PINn
PORTD_PINn
R/W
4
0
CHnMUX[7:0]
(1)
(1)
(1)
(1)
Table
R/W
3
0
5-3. This table is valid for all XMEGA
Event Source
None (manually generated events only)
(Reserved)
(Reserved)
(Reserved)
RTC Overflow
RTC Compare March
(Reserved)
(Reserved)
ACA Channel 0
ACA Channel 1
ACA Window
(Reserved)
(Reserved)
(Reserved)
ADCA Channel n (n =0, 1, 2 or 3)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
PORTA Pin n (n= 0, 1, 2 ... or 7)
PORTB Pin n (n= 0, 1, 2 ... or 7)
PORTC Pin n (n= 0, 1, 2 ... or 7)
PORTD Pin n (n= 0, 1, 2 ... or 7)
R/W
2
0
R/W
1
0
XMEGA D
R/W
0
0
CHnMUX
50