ATxmega16D4 Atmel Corporation, ATxmega16D4 Datasheet - Page 213
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ATxmega16D4
Manufacturer Part Number
ATxmega16D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16D4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega16D4-AU
Manufacturer:
Atmel
Quantity:
438
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Manufacturer:
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Quantity:
20 000
Company:
Part Number:
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Manufacturer:
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Quantity:
1 605
Company:
Part Number:
ATxmega16D4-MHR
Manufacturer:
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Quantity:
50
Part Number:
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Manufacturer:
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Quantity:
20 000
18.13 IRCOM Mode of Operation
18.14 Register Description
18.14.1
18.14.2
8210B–AVR–04/10
DATA - USART I/O Data Register
STATUS - USART Status Register
IRCOM mode can be enabled to use the IRCOM Module with the USART. This enables IrDA 1.4
physical compliant modulation and demodulation for baud rates up to 115.2 Kbps. When IRCOM
mode is enabled, Double Transmission Speed cannot be used for the USART.
For devices with more than one USART, IRCOM mode can only be enabled for one USART at a
time. For details refer to
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the
same I/O address referred to as USART Data Register (DATA). The Transmit Data Buffer Reg-
ister (TXB) will be the destination for data written to the DATA Register location. Reading the
DATA Register location will return the contents of the Receive Data Buffer Register (RXB).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to
zero by the Receiver.
The transmit buffer can only be written when the DREIF Flag in the STATUS Register is set.
Data written to DATA when the DREIF Flag is not set, will be ignored by the USART Transmitter.
When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will
load the data into the Transmit Shift Register when the Shift Register is empty. The data is then
transmitted on the TxD pin.
The receive buffer consists of a two level FIFO. The FIFO and the corresponding flags in the
Status Register (STATUS) will change state whenever the receive buffer is accessed (read).
Always read STATUS before DATA in order to get the correct flags.
• Bit 7 - RXCIF: USART Receive Complete Interrupt Flag
This flag is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (i.e., does not contain any unread data). When the Receiver is disabled, the
receive buffer will be flushed and consequently the RXCIF will become zero.
When interrupt-driven data reception is used, the receive complete interrupt routine must read
the received data from DATA in order to clear the RXCIF. If not, a new interrupt will occur
directly after the return from the current interrupt. This flag can also be cleared by writing a one
to its bit location.
Bit
+0x00
Read/Write
Initial Value
Bit
+0x01
Read/Write
Initial Value
RXCIF
R
7
0
R/W
7
0
TXCIF
R/W
6
0
”IRCOM - IR Communication Module” on page
R/W
6
0
DREIF
R
5
1
R/W
5
0
FERR
R
4
0
R/W
4
0
RXB[[7:0]
BUFOVF
TXB[[7:0]
R
3
0
R/W
3
0
PERR
R
2
0
R/W
2
0
1
–
R
0
220.
XMEGA D
R/W
1
0
RXB8
R/W
0
0
STATUS
R/W
0
0
213