ATxmega16D4 Atmel Corporation, ATxmega16D4 Datasheet - Page 203
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ATxmega16D4
Manufacturer Part Number
ATxmega16D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16D4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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Atmel
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Part Number:
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Manufacturer:
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Part Number:
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Quantity:
20 000
18.3.4
18.3.5
8210B–AVR–04/10
Synchronous Clock Operation
SPI Clock Generation
When synchronous mode is used, the XCK pin controls whether the transmission clock is input
(slave mode) or output (master mode). The corresponding port pin must be set to output for
master mode and to input for slave mode. The normal port operation of the XCK pin will be over-
ridden. The dependency between the clock edges and data sampling or data change is the
same. Data input (on RxD) is sampled at the opposite XCK clock edge of the edge where data
output (TxD) is changed.
Figure 18-3. Synchronous Mode XCKn Timing.
Using the Inverted I/O (INVEN) setting in the Pin Configuration Register for the corresponding
XCK port pin, it is selectable which XCK clock edge is used for data sampling and which is used
for data change. If inverted I/O is disabled (INVEN=0) data will be changed at rising XCK clock
edge and sampled at falling XCK clock edge. If inverted I/O is enabled (INVEN=1) data will be
changed at falling XCK clock edge and sampled at rising XCK clock edge. For more details, see
in “I/O Ports” on page 106.
For SPI operation only master mode with internal clock generation is supported. This is identical
to the USART synchronous master mode and the baud rate or BSEL setting are calculated by
using the same equations, see
There are four combinations of the XCK (SCK) clock phase and polarity with respect to serial
data, and these are determined by the Clock Phase (UCPHA) control bit and the Inverted I/O pin
(INVEN) setting. The data transfer timing diagrams are shown in
bits are shifted out and latched in on opposite edges of the XCK signal, ensuring sufficient time
for data signals to stabilize. The UCPHA and INVEN settings are summarized in
page
Receiver and Transmitter.
Table 18-2.
SPI Mode
203. Changing the setting of any of these bits during transmission will corrupt for both the
0
1
2
3
INVEN and UCPHA Functionality
INVEN = 1
INVEN = 0
INVEN
0
0
1
1
RxD / TxD
RxD / TxD
XCK
XCK
Table 18-1 on page
UCPHA
0
1
0
1
Leading Edge
Rising, Sample
Rising, Setup
Falling, Sample
Falling, Setup
202.
Figure 18-4 on page
Sample
Sample
Trailing Edge
Falling, Setup
Falling, Sample
Rising, Setup
Rising, Sample
XMEGA D
Table 18-2 on
204. Data
203