ATxmega16D4 Atmel Corporation, ATxmega16D4 Datasheet - Page 231
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ATxmega16D4
Manufacturer Part Number
ATxmega16D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16D4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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20.6
20.7
20.8
20.8.1
8210B–AVR–04/10
Compare function
Starting a conversion
ADC Clock and Conversion Timing
Single conversion without gain
The ADC has a built in 12-bit compare function. The ADC compare register can hold a 12-bit
value that represent an analog threshold voltage. The ADC can be configured to automatically
compare its result with this 12-bit compare value to give an interrupt or event only when the
result is above or below the threshold.
Before a conversion is started, the desired input source must be selected for the ADC. An ADC
conversion can either be started by the application software writing to the start conversion bit, or
from any of the events in the Event System.
The ADC is clocked from the Peripheral Clock. The ADC can prescale the Peripheral Clock to
provide an ADC Clock (Clk
Figure 20-12. ADC Prescaler
The maximum ADC sample rate is given by the ADC clock frequency (f
ple a new measurement once the previous conversion is done. The propagation delay of an
ADC measurement is given by:
RES is the resolution, 8- or 12-bit. The propagation delay will increase by one, two or three extra
ADC clock cycles if the Gain Stage (GAIN) is used, according to the following gain settings:
Figure 20-13 on page 232
ing of the start conversion bit, or the event triggering the conversion (START), must occur
minimum one peripheral clock cycles before the ADC clock cycle where the conversion actually
start (indicated with the grey slope of the START trigger).
Propagation Delay =
• GAIN = 1 for 2x and 4x gain settings
• GAIN = 2 for 8x and 16x gain settings
• GAIN = 3 for 32x and 64x gain settings
1
----------------------------------------- -
+
RES
---------- -
2
PRESCALER[2:0]
f
ADC
ADC
shows the ADC timing for a single conversion without gain. The writ-
+
Clk
GAIN
) that is within the minimum and maximum frequency for the ADC.
PER
9-bit ADC Prescaler
Clk
ADC
ADC
). The ADC can sam-
XMEGA D
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