ATxmega128D4 Atmel Corporation, ATxmega128D4 Datasheet - Page 237
ATxmega128D4
Manufacturer Part Number
ATxmega128D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128D4
Flash (kbytes)
128 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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20.12.5
8210B–AVR–04/10
PRESCALER - ADC Clock Prescaler register
• Bits 7:6 - Reserved
These bits are unused and reserved for future use. For compatibility reasons, always write these
bits to zero when this register is written.
• Bits 5:3 - EVSEL[2:0]: event channel input select
These bits define which event channel should trigger the ADC. See
Table 20-3.
• Bits 2:1 - Reserved
These bits are unused and reserved for future use. For compatibility reasons, always write these
bits to zero when this register is written.
• Bits 0 - EVACT0: ADC Event Mode
Setting this bit to one will enable the event line defined by EVSEL to trigger the conversion. Writ-
ing this bit to zero disable ADC event triggering.
• Bits 7:3 - Reserved
These bits are reserved and will always read as zero. For compatibility reasons always write
these bits to zero when this register is written.
• Bits 2:0 - PRESCALER[2:0]: ADC Prescaler configuration
These bits define the ADC clock relative to the Peripheral clock, according to
page
Table 20-4.
Bit
+0x04
Read/Write
Initial Value
PRESCALER[2:0]
EVSEL[2:0]
237.
000
001
010
011
111
000
001
010
011
100
R
7
–
0
ADC Event Line Select
ADC Prescaler settings
R
6
–
0
Group Configuration
Group Configuration
R
5
–
0
0
1
2
3
DIV16
DIV32
DIV64
DIV4
DIV8
R
4
–
0
Selected event lines
Event channel 0 selected inputs
Event channel 1 as selected input
Event channel 2 as selected input
Event channel 3 as selected input
Reserved
R
3
–
0
R/W
2
0
System clock division factor
PRESCALER[2:0]
Table 20-3 on page
R/W
1
0
16
32
64
4
8
XMEGA D
R/W
0
0
Table 20-4 on
PRESCALER
237.
237
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