ATtiny24A Atmel Corporation, ATtiny24A Datasheet - Page 15

• Manufacturer Part Number: ATtiny24A
• Manufacturer: Atmel Corporation

Specifications of ATtiny24A

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

5. Memories
5.1
5.2
8183D–AVR–04/11
In-System Re-programmable Flash Program Memory
SRAM Data Memory
This section describes the different memories in the ATtiny24A/44A/84A. The AVR architecture
has two main memory spaces, the Data memory and the Program memory space. In addition,
the ATtiny24A/44A/84A features an EEPROM Memory for data storage. All three memory
spaces are linear and regular.
The ATtiny24A/44A/84A contains 2K/4K/8K byte On-chip In-System Reprogrammable Flash
memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is orga-
nized as 1024/2048/4096 x 16.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The
ATtiny24A/44A/84A Program Counter (PC) is 10/11/12 bits wide, thus addressing the
1024/2048/4096 Program memory locations.
detailed description on Flash data serial downloading using the SPI pins.
Constant tables can be allocated within the entire Program memory address space (see instruc-
tions LPM – Load Program Memory and SPM – Store Program Memory).
Timing diagrams for instruction fetch and execution are presented in
ing” on page
Figure 5-1.
Figure 5-2 on page 16
The lower data memory locations address both the Register File, the I/O memory and the inter-
nal data SRAM. The first 32 locations address the Register File, the next 64 locations the
standard I/O memory, and the last 128/256/512 locations address the internal data SRAM.
The five different addressing modes for the Data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
10.
Program Memory Map
shows how the ATtiny24A/44A/84A SRAM Memory is organized.
Program Memory
“Memory Programming” on page 158
0x03FF/0x07FF/0x0FFF
0x0000
ATtiny24A/44A/84A
“Instruction Execution Tim-
contains a
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