ATtiny13 Atmel Corporation, ATtiny13 Datasheet - Page 76
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ATtiny13
Manufacturer Part Number
ATtiny13
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny13
Flash (kbytes)
1 Kbytes
Pin Count
8
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.06
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
2
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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12. Timer/Counter Prescaler
12.1
12.2
12.3
76
Overview
Prescaler Reset
External Clock Source
ATtiny13
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock select, the state
of the prescaler will have implications for situations where a prescaled clock is used. One exam-
ple of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 >
CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count
occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64,
256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program
execution.
An external clock source applied to the T0 pin can be used as Timer/Counter clock (clk
T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector.
a functional equivalent block diagram of the T0 synchronization and edge detector logic. The
registers are clocked at the positive edge of the internal system clock (
parent in the high period of the internal system clock.
The edge detector generates one clk
= 6) edge it detects.
Figure 12-1. T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T0 has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
CLK_I/O
Tn
clk
I/O
/1024.
D
LE
CLK_I/O
Q
ExtClk
Synchronization
). Alternatively, one of four taps from the prescaler can be used as a
D
< f
clk_I/O
Q
/2) given a 50/50% duty cycle. Since the edge detector uses
T
0
pulse for each positive (CSn2:0 = 7) or negative (CSn2:0
CLK_I/O
D
Figure 12-1 on page 76
Q
/8, f
CLK_I/O
clk
I/O
Edge Detector
). The latch is trans-
/64, f
CLK_I/O
2535J–AVR–08/10
Tn_sync
(To Clock
Select Logic)
T0
/256, or
shows
). The