ATtiny13 Atmel Corporation, ATtiny13 Datasheet - Page 47

• Manufacturer Part Number: ATtiny13
• Manufacturer: Atmel Corporation

Specifications of ATtiny13

• Flash (kbytes): 1 Kbytes
• Pin Count: 8
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 6
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.06
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

9.3.3
9.3.4
2535J–AVR–08/10
GIFR – General Interrupt Flag Register
PCMSK – Pin Change Mask Register
• Bits 7, 4:0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
• Bit 5 – PCIF: Pin Change Interrupt Flag
When a logic change on any PCINT5:0 pin triggers an interrupt request, PCIF becomes set
(one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bits 7, 6 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bits 5:0 – PCINT5:0: Pin Change Enable Mask 5:0
Each PCINT5:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
If PCINT5:0 is set and the PCIE bit in GIMSK is set, pin change interrupt is enabled on the cor-
responding I/O pin. If PCINT5:0 is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R
R
7
–
0
7
–
0
INTF0
R/W
R
6
0
6
–
0
PCINT5
PCIF
R/W
R/W
5
0
5
0
PCINT4
R/W
R
4
0
4
–
0
PCINT3
R/W
R
3
0
3
–
0
PCINT2
R/W
2
0
R
2
–
0
PCINT1
R/W
1
0
R
1
–
0
PCINT0
R/W
0
0
R
0
–
0
PCMSK
GIFR
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