ATmega644 Atmel Corporation, ATmega644 Datasheet - Page 260

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ATmega644

Manufacturer Part Number
ATmega644
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega644

Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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23.3.1
23.3.2
Version
Part Number
Manufacturer ID
23.3.3
260
ATmega644
Bypass Register
Device Identification Register
Reset Register
The Bypass Register consists of a single Shift Register stage. When the Bypass Register is
selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR
controller state. The Bypass Register can be used to shorten the scan chain on a system when
the other devices are to be tested.
Figure 23-1
Figure 23-1. The Format of the Device Identification Register
Version is a 4-bit number identifying the revision of the component. The JTAG version number
follows the revision of the device. Revision A is 0x0, revision B is 0x1 and so on.
The part number is a 16-bit code identifying the component. The JTAG Part Number for
ATmega644 is listed in
The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID
for ATMEL is listed in
The Reset Register is a test Data Register used to reset the part. Since the AVR tri-states Port
Pins when reset, the Reset Register can also replace the function of the unimplemented optional
JTAG instruction HIGHZ.
A high value in the Reset Register corresponds to pulling the external Reset low. The part is
reset as long as there is a high value present in the Reset Register. Depending on the fuse set-
tings for the clock options, the part will remain reset for a reset time-out period (refer to
Sources” on page
not latched, so the reset will take place immediately, as shown in
Figure 23-2. Reset Register
Bit
Device ID
From Other Internal and
External Reset Sources
shows the structure of the Device Identification Register.
MSB
31
Version
4 bits
28) after releasing the Reset Register. The output from this Data Register is
Table 25-6 on page
28
Table 25-6 on page
From
ClockDR · AVR_RESET
TDI
27
Part Number
16 bits
D
287.
287.
Q
TDO
To
12
11
Figure
Manufacturer ID
11 bits
23-2.
Internal reset
2593N–AVR–07/10
1
LSB
1-bit
”Clock
1
0

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