ATmega48 Automotive Atmel Corporation, ATmega48 Automotive Datasheet - Page 73

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ATmega48 Automotive

Manufacturer Part Number
ATmega48 Automotive
Description
Manufacturer
Atmel Corporation

Specifications of ATmega48 Automotive

Flash (kbytes)
4 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
256
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
7530I–AVR–02/10
Table 10-4.
Notes:
Table 10-5.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
1. INTRC means that one of the internal RC Oscillators are selected (by the CKSEL fuses),
EXTCK means that external clock is selected (by the CKSEL fuses).
PB3/MOSI/
OC2/PCINT3
SPE • MSTR
PORTB3 • PUD
SPE • MSTR
0
SPE • MSTR +
OC2A ENABLE
SPI MSTR OUTPUT
+ OC2A
PCINT3 • PCIE0
1
PCINT3 INPUT
SPI SLAVE INPUT
Oscillator Output
PB7/XTAL2/
TOSC2/PCINT7
INTRC • EXTCK+
AS2
0
INTRC • EXTCK+
AS2
0
0
0
INTRC • EXTCK +
AS2 + PCINT7 •
PCIE0
(INTRC + EXTCK) •
AS2
PCINT7 INPUT
Overriding Signals for Alternate Functions in PB7..PB4
Overriding Signals for Alternate Functions in PB3..PB0
(1)
PB6/XTAL1/
TOSC1/PCINT6
INTRC + AS2
0
INTRC + AS2
0
0
INTRC + AS2 +
PCINT6 • PCIE0
INTRC • AS2
PCINT6 INPUT
Oscillator/Clock
Input
PB2/SS/
OC1B/PCINT2
SPE • MSTR
PORTB2 • PUD
SPE • MSTR
0
OC1B ENABLE
OC1B
PCINT2 • PCIE0
1
PCINT2 INPUT
SPI SS
0
ATmega48/88/168 Automotive
(1)
PB5/SCK/
PCINT5
0
SCK OUTPUT
PCINT5 • PCIE0
1
PCINT5 INPUT
SCK INPUT
PB1/OC1A/
PCINT1
0
0
0
0
OC1A ENABLE
OC1A
PCINT1 • PCIE0
1
PCINT1 INPUT
SPE • MSTR
PORTB5 • PUD
SPE • MSTR
SPE • MSTR
SPE • MSTR
PCINT4 • PCIE0
PB0/ICP1/
PCINT0
0
0
0
0
0
0
PCINT0 • PCIE0
1
PCINT0 INPUT
ICP1 INPUT
PB4/MISO/
PCINT4
SPE • MSTR
PORTB4 • PUD
SPE • MSTR
0
SPI SLAVE
OUTPUT
1
PCINT4 INPUT
SPI MSTR INPUT
73

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