ATmega324P Automotive Atmel Corporation, ATmega324P Automotive Datasheet - Page 208

• Manufacturer Part Number: ATmega324P Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega324P Automotive

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.8.4
18.8.5
208
ATmega164P/324P/644P
UCSRnC – USART MSPIM Control and Status Register n C
UBRRnL and UBRRnH –USART MSPIM Baud Rate Registers
• Bit 7:6 - UMSELn1:0: USART Mode Select
These bits select the mode of operation of the USART as shown in
USART Control and Status Register n C” on page 192
operation. The MSPIM is enabled when both UMSELn bits are set to one. The UDORDn,
UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM is enabled.
Table 18-4.
• Bit 5:3 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnC is written.
• Bit 2 - UDORDn: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the
data word is transmitted first. Refer to the Frame Formats section page 4 for details.
• Bit 1 - UCPHAn: Clock Phase
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last)
edge of XCKn. Refer to the SPI Data Modes and Timing section page 4 for details.
• Bit 0 - UCPOLn: Clock Polarity
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and
UCPHAn bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and
Timing section page 4 for details.
The function and bit description of the baud rate registers in MSPI mode is identical to normal
USART operation. See
Bit
Read/Write
Initial Value
UMSELn1
0
0
1
1
UMSELn Bits Settings
UMSELn1
R/W
7
0
“UBRRnL and UBRRnH – USART Baud Rate Registers” on page
1
0
1
UMSELn0
0
UMSELn0
R/W
6
0
R
5
0
-
R
4
0
-
Mode
Asynchronous USART
(Reserved)
Master SPI (MSPIM)
Synchronous USART
R
3
0
-
for full description of the normal USART
UDORDn
R/W
2
1
Table
UCPHAn
R/W
1
1
18-4. See
UCPOLn
R/W
0
0
7674F–AVR–09/09
“UCSRnC –
UCSRnC
194.