ATmega324P Automotive Atmel Corporation, ATmega324P Automotive Datasheet - Page 175
ATmega324P Automotive
Manufacturer Part Number
ATmega324P Automotive
Description
Manufacturer
Atmel Corporation
Specifications of ATmega324P Automotive
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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17.4.3
17.4.4
7674F–AVR–09/09
External Clock
Synchronous Clock Operation
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to
External clock input from the XCKn pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process intro-
duces a two CPU clock period delay and therefore the maximum external XCKn clock frequency
is limited by the following equation:
Note that f
add some margin to avoid possible loss of data due to frequency variations.
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxDn) is sampled at the
opposite XCKn clock edge of the edge the data output (TxDn) is changed.
Figure 17-3. Synchronous Mode XCKn Timing.
The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is
used for data change. As
be changed at rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data
will be changed at falling XCKn edge and sampled at rising XCKn edge.
UCPOL = 1
UCPOL = 0
osc
depends on the stability of the system clock source. It is therefore recommended to
Figure 17-2 on page 173
RxD / TxD
RxD / TxD
XCK
XCK
Figure 17-3 on page 175
for details.
f
XCK
f
---------- -
ATmega164P/324P/644P
OSC
4
shows, when UCPOLn is zero the data will
Sample
Sample
175
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