ATmega324P Automotive Atmel Corporation, ATmega324P Automotive Datasheet - Page 14

• Manufacturer Part Number: ATmega324P Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega324P Automotive

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.5.1
5.6
14
Instruction Execution Timing
ATmega164P/324P/644P
SPH and SPL – Stack Pointer High and Stack pointer Low
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 5-4 on page 14
by the Harvard architecture and the fast-access Register File concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Figure 5-4.
Figure 5-5
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
shows the internal timing concept for the Register File. In a single clock cycle an ALU
The Parallel Instruction Fetches and Instruction Executions
SP7
R/W
15
R
–
7
0
1
clk
CPU
shows the parallel instruction fetches and instruction executions enabled
SP6
R/W
14
R
–
6
0
1
SP5
R/W
CPU
13
R
–
5
0
1
T1
, directly generated from the selected clock source for the
SP12
R/W
R/W
SP4
12
4
1
1
T2
SP11
SP3
R/W
R/W
11
3
0
1
SP10
R/W
R/W
SP2
10
2
0
1
T3
SP9
SP1
R/W
R/W
9
1
0
1
R/W
R/W
SP8
SP0
8
0
0
1
7674F–AVR–09/09
T4
SPH
SPL