AT83C5136 Atmel Corporation, AT83C5136 Datasheet - Page 127

• Manufacturer Part Number: AT83C5136
• Manufacturer: Atmel Corporation

Specifications of AT83C5136

• Max. Operating Frequency: 32 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Eeprom (bytes): 512
• Operating Voltage (vcc): 2.7 to 3.6
• Timers: 4
• Mask Rom (kbytes): 32
• Watchdog: Yes

7683C–USB–11/07
Table 21-13. UEPRST Register
Reset Value = 00h
Bit Number
7
7
6
5
4
3
2
1
0
-
Mnemonic
EP5RST
EP4RST
EP3RST
EP2RST
EP1RST
EP0RST
UEPRST (S:D5h)
USB Endpoint FIFO Reset Register
Bit
6
-
-
-
Description
Reserved
The value read from this bit is always 0. Do not set this bit.
Reserved
The value read from this bit is always 0. Do not set this bit.
Endpoint 5 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 4 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 3 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 2 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 1 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 0 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
EP5RST
5
EP4RST
4
EP3RST
3
EP2RST
AT83C5134/35/36
2
EP1RST
1
EP0RST
0
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