AT83C5136 Atmel Corporation, AT83C5136 Datasheet - Page 106

• Manufacturer Part Number: AT83C5136
• Manufacturer: Atmel Corporation

Specifications of AT83C5136

• Max. Operating Frequency: 32 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Eeprom (bytes): 512
• Operating Voltage (vcc): 2.7 to 3.6
• Timers: 4
• Mask Rom (kbytes): 32
• Watchdog: Yes

Figure 21-6. Endpoint FIFO Configuration
21.3.2
21.3.3
21.4
106
Bulk/Interrupt Transactions
AT83C5134/35/36
Read Data FIFO
Write Data FIFO
Endpoint 0
Endpoint 5
The read access for each OUT endpoint is performed using the UEPDATX register.
After a new valid packet has been received on an Endpoint, the data are stored into the FIFO
and the byte counter of the endpoint is updated (UBYCTLX and UBYCTHX registers). The firm-
ware has to store the endpoint byte counter before any access to the endpoint FIFO. The byte
counter is not updated when reading the FIFO.
To read data from an endpoint, select the correct endpoint number in UEPNUM and read the
UEPDATX register. This action automatically decreases the corresponding address vector, and
the next data is then available in the UEPDATX register.
The write access for each IN endpoint is performed using the UEPDATX register.
To write a byte into an IN endpoint FIFO, select the correct endpoint number in UEPNUM and
write into the UEPDATX register. The corresponding address vector is automatically increased,
and another write can be carried out.
Warning 1: The byte counter is not updated.
Warning 2: Do not write more bytes than supported by the corresponding endpoint.
Bulk and Interrupt transactions are managed in the same way.
UEPSTA0
UEPSTA5
UBYCTH0
UBYCTH5
UEPCON0
UEPCON5
UBYCTL0
UBYCTL5
UEPDAT0
UEPDAT5
UEPNUM
0
1
2
3
4
5
X
UEPSTAX
UBYCTHX
SFR registers
UEPCONX
UBYCTLX
7683C–USB–11/07
UEPDATX