AT32UC3B0512 Atmel Corporation, AT32UC3B0512 Datasheet - Page 438
AT32UC3B0512
Manufacturer Part Number
AT32UC3B0512
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B0512
Flash (kbytes)
512 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3B0128 PDF datasheet #4
- AT32UC3B0128 PDF datasheet #5
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22.8.2.19
Register Name:
Access Type:
Offset:
Reset Value:
• CHBYTELENGTH: Channel Byte Length
• BURSTLOCKEN: Burst Lock Enable
• DESCLDIRQEN: Descriptor Loaded Interrupt Enable
• EOBUFFIRQEN: End of Buffer Interrupt Enable
• EOTIRQEN: End of USB Transfer Interrupt Enable
• DMAENDEN: End of DMA Buffer Output Enable
32059L–AVR32–01/2012
BURSTLOCKEN
31
23
15
7
-
This field determines the total number of bytes to be transferred for this buffer.
The maximum channel transfer size 64kB is reached when this field is zero (default value).
If the transfer size is unknown, the transfer end is controlled by the peripheral and this field should be written to zero.
This field can be written or descriptor loading only after the UDDMAnSTATUS.CHEN bit has been cleared, otherwise this field is
ignored.
1: The USB data burst is locked for maximum optimization of HSB busses bandwidth usage and maximization of fly-by duration.
0: The DMA never locks the HSB access.
1: The Descriptor Loaded interrupt is enabled.This interrupt is generated when a Descriptor has been loaded from the system
bus.
0: The Descriptor Loaded interrupt is disabled.
1: The end of buffer interrupt is enabled.This interrupt is generated when the channel byte count reaches zero.
0: The end of buffer interrupt is disabled.
1: The end of usb OUT data transfer interrupt is enabled. This interrupt is generated only if the BUFFCLOSEINEN bit is set.
0: The end of usb OUT data transfer interrupt is disabled.
Writing a one to this bit will properly complete the usb transfer at the end of the dma transfer.
For IN endpoint, it means that a short packet (but not a Zero Length Packet) will be sent to the USB line to properly closed the
usb transfer at the end of the dma transfer.
For OUT endpoint, it means that all the banks will be properly released. (NBUSYBK=0) at the end of the dma transfer.
Device DMA Channel n Control Register
DESCLDIRQEN
30
22
14
6
-
UDDMAnCONTROL, n in [1..6]
Read/Write
0x0318 + (n - 1) * 0x10
0x00000000
EOBUFFIRQEN
29
21
13
5
-
EOTIRQEN
CHBYTELENGTH[15:8]
CHBYTELENGTH[7:0]
28
20
12
4
-
DMAENDEN
27
19
11
3
-
BUFFCLOSE
INEN
26
18
10
2
-
LDNXTCH
DESCEN
25
17
9
1
-
CHEN
24
16
8
0
-
438
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