RS8250EBGC Conexant Systems, Inc., RS8250EBGC Datasheet

no-image

RS8250EBGC

Manufacturer Part Number
RS8250EBGC
Description
ATM Physical Interface Device - ATM PHY
Manufacturer
Conexant Systems, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
RS8250EBGC
Manufacturer:
MNDSPEED
Quantity:
5
Part Number:
RS8250EBGC
Manufacturer:
CONEXANT
Quantity:
1 831
R O C K W E L L
S E M I C O N D U C T O R
S Y S T E M S
Network
access
RS8250/1/2/3/4/5
ATM Physical Interface
Devices - ATM PHY
datasheet
P R O V I D I N G
H I G H
S P E E D
M U L T I M E D I A
C O N N E C T I O N S
September 1998

Related parts for RS8250EBGC

RS8250EBGC Summary of contents

Page 1

Network access ...

Page 2

Preliminary Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY The RS825x is a family of six 155 Mbps (OC-3/STM-1) ATM-SONET Physical ...

Page 3

... Ordering Information Manufacturing Model Number Part Number RS8250EBGC 28250-14 RS8251ETFB 28251-13 RS8252EBG R7171-11 RS8253EBG R7172-11 RS8254EBG R7173-11 RS8255EBG R7174-11 RS8254EBGB R7173-12 Copyright © 1998 Rockwell Semiconductor Systems, Inc. All rights reserved. Print date: September 1998 Rockwell Semiconductor Systems, Inc. reserves the right to make changes to its products or specifications to improve performance, reliability, or manufacturability. Information furnished is believed to be accurate and reliable. However, no responsibility is assumed for its use ...

Page 4

RS825x Features Line Interface • ATM Forum WIRE interface specification compliant • PECL I/O, compatible with PMD optical and UTP interface devices • Clock recovery from NRZ input data • Recovery of receive-octet alignment and octet clock from F6/28 framing ...

Page 5

Sonet Framer Functions • Recovers frame location using F6/28 framing pattern. • Processes pointer to locate payload envelope. • Provides OOF, LOP, and AIS status. • Provides frame and payload position information to other blocks. • Generates clocks and frame ...

Page 6

Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 7

Table of Contents 2.4.3.6 Line RDI/AIS Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 8

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 3.2.3 RS825x PMD Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 9

Table of Contents 0x07—ERRPAT (Error Pattern Control Register ...

Page 10

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x4F—OOFCNT (OOF Event Counter ...

Page 11

Table of Contents B.3 RS8254/5 Electrical and Mechanical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 12

List of Figures Figure 1-1. RS825x Connected to a SAR (RS8234/ ...

Page 13

Figure 5-10. Receive UTOPIA Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 14

List of Tables Table 1-1. RS8251 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 15

Table 5-15. PECL-Output DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 16

Product Description The RS825x ATM Physical Layer Interface (PHY) device is a transmitter/receiver, which performs the Transmission Convergence (TC) sublayer function of converting SONET/SDH frames to ATM cells and vice versa. The RS825x family consists of 6 devices ...

Page 17

Product Description 1.1 RS825x Features 1.1 RS825x Features The RS825x, operating 155 Mbps (duplex), provides a single-access ATM service termination for User-to-Network Interfacing (UNI) and Network-to-Network Interfacing (NNI) in conformance with the ATM Forum UNI Specification ...

Page 18

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 1.2 Applications Overview The RS825x can be used in a number of applications including: • ATM LANs over optical fibers • Workstations and PC Network Interface Cards (NICs) • LAN switches and hubs • ...

Page 19

Product Description 1.3 Logic Diagram 1.3 Logic Diagram Figure 1 logic diagram of the RS825x’s functional blocks. There are seven general purpose Clock and Control pins. The PMD interface consists of 12 pins. The Microprocessor interface consists ...

Page 20

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 1.4 Pin Diagram and Definitions Figure 1 pinout diagram for the RS8251 ATM Transmitter/Receiver single CMOS integrated circuit packaged in a 128-pin TQFP. All unused input pins should be ...

Page 21

Product Description 1.4 Pin Diagram and Definitions Table 1-2. RS8251 Pin Definitions (1 of 10) Pin Label Signal Name Reset* Device Reset OneSecIn One-Second Strobe OneSecOut One-Second Output TxFrameRef Transmit Frame Clock RxFrameRef Receive Frame Clock 8kHzIn 8 kHz ...

Page 22

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table 1-2. RS8251 Pin Definitions (2 of 10) Pin Label Signal Name LTxData- Line Transmit Output Negative Polarity LTxData+ Line Transmit Output Positive Polarity LRxClk- Line Receive Clock Negative LRxClk+ Line Receive Clock Positive ...

Page 23

Product Description 1.4 Pin Diagram and Definitions Table 1-2. RS8251 Pin Definitions (3 of 10) Pin Label Signal Name MSyncMode Microprocessor Synchronous/Asy nchronous Bus Mode Select MClk, Microprocessor MAcsSel Clock, Access Time Select MCs* Microprocessor Chip Select MW/R*, Microprocessor ...

Page 24

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table 1-2. RS8251 Pin Definitions (4 of 10) Pin Label Signal Name MAs*, MWr* Microprocessor Address Strobe, Write Control MAddr[6] Microprocessor Address Bus MAddr[5] MAddr[4] MAddr[3] MAddr[2] MAddr[1] MAddr[0] MData[7] Microprocessor Data Bus MData[6] ...

Page 25

Product Description 1.4 Pin Diagram and Definitions Table 1-2. RS8251 Pin Definitions (5 of 10) Pin Label Signal Name TRST* Test Reset TCK Test Clock TMS Test Mode Select TDI Test Data Input TDO Test Data Output 1-10 ATM ...

Page 26

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table 1-2. RS8251 Pin Definitions (6 of 10) Pin Label Signal Name StatOut[7] Status Outputs StatOut[6] StatOut[5] StatOut[4] StatOut[3] StatOut[2] StatOut[1] StatOut[0] No. Type I/O 126 TTL O This pin reflects either the value ...

Page 27

Product Description 1.4 Pin Diagram and Definitions Table 1-2. RS8251 Pin Definitions (7 of 10) Pin Label Signal Name TxDL Transmit Data Link Input UTxClk UTOPIA Transmit Clock UTxEnb* UTOPIA Transmit Enable UTxAddr[0] LSB UTxAddr[1] UTOPIA Transmit UTxAddr[2] Address ...

Page 28

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table 1-2. RS8251 Pin Definitions (8 of 10) Pin Label Signal Name UTxSOC UTOPIA Transmit Start of Cell UTxClAv UTOPIA Transmit Cell Available URxClk UTOPIA Receive Clock URxEnb* UTOPIA Receive Enable URxAddr[0] UTOPIA Receive ...

Page 29

Product Description 1.4 Pin Diagram and Definitions Table 1-2. RS8251 Pin Definitions (9 of 10) Pin Label Signal Name URxData[0] UTOPIA Receive Data Bus URxData[1] URxData[2] URxData[3] URxData[4] RxData[5] URxData[6] URxData[7] URxData[8] URxData[9] URxData[10] URxData[11] URxData[12] URxData[13] URxData[14] URxData[15] ...

Page 30

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table 1-2. RS8251 Pin Definitions (10 of 10) Pin Label Signal Name URxClAv UTOPIA Receive Cell Available PWR Supply Voltage Analog PWR Analog Supply Voltage GND Ground Analog GND Analog Ground V Electrostatic GG ...

Page 31

Product Description 1.5 Block Diagram and Descriptions 1.5 Block Diagram and Descriptions Figure 1 detailed block diagram of the RS825x. When traffic is transmitted from the host system, octet-wide or 16-bit data enters the RS825x via the ...

Page 32

Functional Description This chapter describes the RS825x architecture and functional blocks. Figure 2-1 shows the RS825x’s transmit signal path. The RS825x calculates the HEC for incoming ATM cells from the UTOPIA interface and inserts it into the fifth octet ...

Page 33

Functional Description 2.1 Line Interface Figure 2-2 shows the RS825x’s receive signal path. The RS825x recovers the clock from the incoming data stream. The serial data stream is converted to parallel and passed to the framer block where overhead ...

Page 34

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table 2-1. Single-Ended PECL Table Symbol V sref typical PMD/PECL interface is shown in Figure 2-3. This block diagram assumes a 3.3 V PMD. Resistors ...

Page 35

Functional Description 2.2 Clock Circuits Table 2-2. PECL Input Logic Table The output logic table for this PECL interface is shown in Table 2-3. Table 2-3. PECL Output Logic Table This high-impedance output condition necessitates the use of a ...

Page 36

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY This clock meets jitter tolerance and jitter transfer specifications according to Bellcore GR-253 (see Figure 2-4). Jitter tolerance is defined as how much jitter the receiver can tolerate and still extract the correct data ...

Page 37

Functional Description 2.4 SONET/SDH Framer and Overhead Processor 2.4 SONET/SDH Framer and Overhead Processor Rockwell’s RS825x SONET/SDH framer has an extensive SONET overhead processing section with external access for D1-D3 and D4-D12 Data Link message processing. The framer provides ...

Page 38

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Payload Envelope (SPE). In SDH, the payload is called Virtual Container 4 (VC4). This document uses SPE to refer to the payload in either format. Figure 2-6. STS-3c/STM-1 Frame Timing Transport Overhead Time in ...

Page 39

Functional Description 2.4 SONET/SDH Framer and Overhead Processor Table 2-4. SONET Overhead Byte Definitions and Values Layer Byte H1, H2, H3 B2-1, B2-2, B2-3 K1, K2 (Bits 1-5) K2 (Bits 6-8) D4-D12 (bits ...

Page 40

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table 2-5. Section Overhead Transmit and Receive Functions A1/A2 B1 D1, D2, D3 (WAN Only 2.4.2.1 A1, A2 The STS-3c/STM-1 framing bytes, A1 and A2, are used to determine ...

Page 41

Functional Description 2.4 SONET/SDH Framer and Overhead Processor receive buffer from the previous message received, an interrupt will appear in register SECINT (0x3D) bit 1. 2.4.2.6 Z0 The Section Growth bytes, Z0 respectively. 2.4.3 Line Overhead The Line Overhead ...

Page 42

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table 2-7. H1, H2, and H3 Functions STS-3c Value Overhead Byte (in Hex) H2-1 Transmit 0A H2-2 Transmit FF H2-3 Transmit FF H3-1 Transmit 00 H3-2 Transmit 00 H3-3 Transmit 00 2.4.3.2 Loss of ...

Page 43

Functional Description 2.4 SONET/SDH Framer and Overhead Processor Table 2-8. SF/SD Threshold Table SF Thresh (Bits 7-4) Detection SD Thresh (Bits 3-0) Threshold ...

Page 44

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Figure 2-7. Switch Initiation Time Graph Switch Initiation Time 2.4.3.5 K1 and K2 The APS Channel bytes, K1 and K2, are allocated for Automatic Protection (WAN only) Switching (APS) signaling between line level entities. ...

Page 45

Functional Description 2.4 SONET/SDH Framer and Overhead Processor 2.4.3.6 Line RDI/AIS The Remote Defect Indication-Line (RDI-L) signal indicates to a Line Detect Terminating Equipment (LTE) that the remote equipment is detecting a defect somewhere along the SONET line. Received ...

Page 46

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table 2-10. Path Overhead Transmit and Receive Functions 2.4.4.1 J1 The Path Trace byte, J1 circular 64-byte buffer, carrying the Path Trace message, so that a receiving Path ...

Page 47

Functional Description 2.4 SONET/SDH Framer and Overhead Processor values that are transmitted for various receiver alarm conditions. The user can override these values by setting AutoPthRDI to 0 and directly writing the desired value to be transmitted into TXPTH ...

Page 48

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY and all the subsequent bits to be scrambled are added, modulo 2, to the output from the x overhead is scrambled. This scrambling occurs just before the signal is passed to the PMD sublayer. ...

Page 49

Functional Description 2.5 ATM Cell Processor 2.5.1.1 HEC Generation In normal operation, the RS825x calculates the HEC for the 4 header bytes of each cell coming from the ATM layer. It then adds the HEC coset and inserts the ...

Page 50

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Figure 2-8. Cell Delineation Process 1 Correct HEC Hunt When in the sync state of cell delineation, cells are passed to the ATM block if the HEC is valid single-bit error in ...

Page 51

Functional Description 2.5 ATM Cell Processor screening, compares the incoming bits to the values in the receive cell header registers. Cells are rejected or accepted based on the bit patterns of their headers. Idle cell rejection is enabled in ...

Page 52

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Descrambling uses the same polynomial to recover the 48-byte cell payload. The descrambler polynomial is self-synchronizing. It can be enabled by writing bit 5 in register CVAL (0x08 2.6 Data Link Interface ...

Page 53

Functional Description 2.6 Data Link Interface 2.6.1 Data Link Transmit The RS825x can insert data into the D1–D12 octets of the outgoing data stream. This function is controlled by EnTxSecDL, bit 6 of the TXSEC, 0x0C register and EnTxLinDL, ...

Page 54

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Figure 2-10. Data Link Receive Timing Diagram t pwh t pwl Data Link Rx clock Data Link Indicator Data Link Rx Data D1,b7 D1,b6 D1, pwh t = 1000 ns ...

Page 55

Functional Description 2.7 UTOPIA Interface the UTOPIA interface, incoming cells are stripped of SONET overhead, converted to ATM formatted cells, and placed in the receive FIFO until sent out. NOTE: 2.7.2 UTOPIA 8-bit and 16-bit Bus Widths The RS825x ...

Page 56

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY NOTE: 2.7.3 UTOPIA Parity The RS825x supports even and odd parity, which is controlled by bit 2 of the UTOP1 register (0x0A). The parity on received data is calculated for either 8 bits or ...

Page 57

Functional Description 2.8 Microprocessor Interface encounter an unacceptable error rate, software can quickly enable the backup PHY and disable the primary PHY, reducing cell loss in the transition. NOTE: 2.7.5 Handshaking The RS825x provides both cell-level and octet-level handshaking ...

Page 58

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY the specific function of each control register. There are two types of status input: live and latched. Live status provides the current status of the device. Latched status is used for rapidly changing states ...

Page 59

Functional Description 2.8 Microprocessor Interface 2.8.4 Interrupts The RS825x’s interrupt indications can be classified as either single-event or dual-event. A single-event interrupt is triggered by a status assertion. A dual-event interrupt is triggered by either a status assertion or ...

Page 60

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Figure 2-11. Interrupt Indication Flow Chart OneSecInt Event Occurs Figure 2-12 shows the registers involved in the interrupt generation process. SECINT, LININT, PTHINT, APSINT, TXCELLINT or RXCELLINT Event Occurs Individual No Interrupt Indication Enabled ...

Page 61

Functional Description 2.8 Microprocessor Interface Figure 2-12. Interrupt Indication Diagram SECINT (0x3D) SigDetInt 7 LOLInt 6 LOSInt 5 OOFInt 4 OR LOFInt 3 2 B1ErrInt 1 SecTraceInt 0 Reserved Outputs Enabled by ENSEC (0x35) PTHINT (0x3F) AIS-PInt 7 RDI-PInt ...

Page 62

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 2.8.4.2 Interrupt When an interrupt occurs on the MInt* pin (pin 6), it could have been generated Servicing by any of 35 events. The RS825x’s interrupt indication process ensures that a maximum of two ...

Page 63

Functional Description 2.9 Loopback Modes Figure 2-13. Near-End Line Loopback Diagram TRST* TDI TCK TMS TDO ATM WIRE Interface JTAG Controller TxDat+/- Transmit TxClkI+/- Line STS-3c/STM-1 TxClkO+/- Interface Transmit Framer Loopback PECL Logic SONET Line Framer Control Level Receive ...

Page 64

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Figure 2-14. UTOPIA Loopback Diagram TRST* TDI TCK TMS TDO ATM WIRE Interface JTAG Controller TxDat+/- Transmit TxClkI+/- Line STS-3c/STM-1 TxClkO+/- Interface Transmit Framer Loopback PECL Logic SONET Line Framer Control Level Receive RxDat+/- ...

Page 65

Functional Description 2.9 Loopback Modes Figure 2-15. Source Loopback Diagram TRST* TDI TCK TMS TDO ATM WIRE Interface JTAG Controller TxDat+/- Transmit TxClkI+/- Line STS-3c/STM-1 TxClkO+/- Interface Transmit Framer Loopback PECL Logic SONET Line Framer Control Level Receive RxDat+/- ...

Page 66

Applications This chapter provides application examples for the RS825x. A system application shows the RS8251 connected in a NIC application using Rockwell’s RS8235 SAR and a Cat 5 PMD. All board layouts, schematics and the parts list are ...

Page 67

Applications 3.1 System Application Figure 3-1. RS8251 and SAR (RS8234/5) Application Diagram RS8234/5 TXD[7:0] TXFLAG* TXEN TXMARK PCI TXPAR Bus CLKD3 RXD[7:0] RXFLAG* RXEN* RXMARK RXPAR PCS* SYSCLK PRST* PDAEN* PFAIL* PAS* PWNR PWAIT* PBLAST* PBE[3:0]* PBSEL[1,0] PADDR[0] PADDR[1] ...

Page 68

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Evaluation board schematics for the RS8235/RS8251 NIC are shown in the three fold-out pages at the end of this chapter. 3.2 PECL Applications This section provides application examples for the PECL interface. 3.2.1 RS825x ...

Page 69

Applications 3.2 PECL Applications 3.2.2 RS825x PMD Inputs When connecting the RS825x 3.3 V PECL outputs PECL inputs, ensure that the lines are properly terminated. In addition, the input voltage levels must be ...

Page 70

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 3.2.3 RS825x PMD Outputs The recommended termination and level shifting circuit for connecting 5.0 V PECL outputs to the RS825x’s 3.3 V PECL inputs is shown in Figure 3-4. The line ...

Page 71

Applications 3.2 PECL Applications 3.2.4 PECL Layout All PECL traces must be treated as transmission lines. Therefore, standard high-speed practices must be followed, including: • Keep traces as short as reasonable. • Do not allow traces to cross discontinuities ...

Page 72

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 3.2.5 The RS825x/RS8235 Network Interface Card Reference Design The following schematic shows a single-port RS8251 implementing the ATM forum standard for 155 Mbps over Cat 5 twisted pair in a network interface card, NIC, ...

Page 73

REVISIONS ZONE LTR DESCRIPTION DATE B BT00-X720 CONTRACT NO. ROCKWELL SEMICONDUCTOR SYSTEMS APPROVALS DATE San Diego, CA 92121 DRAWN DAN SCOTT 7/98 8235/8251 CHECKED PCB:BTOO-D725-003 ENGINEER JEFF MULLIN ASSY:BT00-D720-041 ...

Page 74

A C15 CC + C22 .01 U6 LADDR0 A17 44 44 LADDR1 A16 43 43 LADDR2 3 3 A15 LADDR3 LADDR4 5 ...

Page 75

A +5V NOTE C13 +5V Components marked with # C14 installed for RS8251 rev C +5V C20 Components marked with 1 +5V removed for RS8251 rev C C18 R17 TXIN+ TPOUT+ 23 TXIN- TPOUT+ TPOUT- SD+ 24 ...

Page 76

Applications 3.2 PECL Applications 3-8 ATM Physical Interface Devices—ATM PHY Preliminary N825xDSA RS8250/1/2/3/4/5 ...

Page 77

Registers The RS825x registers are used to control and observe the device’s operations. A list of these control and status registers, buffers, and counters is presented in Table 4-1. All registers are 8 bits wide. All control registers ...

Page 78

Registers Table 4-1. Control and Status Registers ( Address Name Type TXK2 0x11 R/W (WAN) TXS1 0x12 R/W (WAN) 0x13 TXC2 R/W RXK1 0x14 R (WAN) RXK2 0x15 R (WAN)Low Byte RXS1 0x16 R (WAN) 0x17 — ...

Page 79

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table 4-1. Control and Status Registers ( Address Name Type 0x2C RXIDL1 R/W 0x2D RXIDL2 R/W 0x2E RXIDL3 R/W 0x2F RXIDL4 R/W 0x30 IDLMSK1 R/W 0x31 IDLMSK2 R/W 0x32 IDLMSK3 R/W 0x33 ...

Page 80

Registers Table 4-1. Control and Status Registers ( Address Name Type 0x47 RXPTH R 0x48 TXCELL R 0x49 RXCELL R RXAPS 0x4A R (WAN) 0x4B — — 0x4C LOCDCNT R 0x4D CORRCNT R 0x4E UNCCNT R 0x4F ...

Page 81

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table 4-1. Control and Status Registers ( Address Name Type 0x61 TXCNTM R 0x62 TXCNTH R 0x63 — — 0x64 RXCNTL R 0x65 RXCNTM R 0x66 RXCNTH R 0x67 — — 0x68 ...

Page 82

Registers 4.1 General Use Registers 4.1 General Use Registers This section describes several registers that are used for basic functions of the device. 0x00—GEN (General Control Register) The GEN register controls the receiver hold input pin, one-second latch enables, ...

Page 83

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x01—CLKREC (Clock Recovery Control Register) The CLKREC register controls the clock recovery and loopback testing capabilities of the device. Bit Default Name 7 0 InvTxClk 6 0 InvRxClk 5 0 ExtClkRec 4 0 TxClkSel(1) ...

Page 84

Registers 4.1 General Use Registers 0x02—OUTSTAT (Output Pin Control Register) The OUTSTAT register contains the values that will be reflected on the StatOut[7:0] pins when register 0x00 (GEN), bit 2 is written to “1,” enabling Status Output Pin Mode. ...

Page 85

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 4.2 Cell Transmit Control Registers This section describes the control registers used for transmission of traffic. 0x04—CGEN (Cell Generation Control Register) The CGEN register controls the device’s cell generation functions. Bit Default Name 7 ...

Page 86

Registers 4.2 Cell Transmit Control Registers 0x05—IDLPAY (Transmit Idle Cell Payload Control Register) The IDLPAY register contains the transmit idle cell payload. Bit Default Name 7 0 IdlPay[ IdlPay[ IdlPay[ IdlPay[ ...

Page 87

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x1D—TXHDR2 (Transmit Cell Header Control Register 2) The TXHDR2 register contains the second byte of the Transmit Cell Header. (See TXHDR1.) Bit Default Name 7 0 TxHdr2[ TxHdr2[ TxHdr2[5] 4 ...

Page 88

Registers 4.2 Cell Transmit Control Registers 0x1F—TXHDR4 (Transmit Cell Header Control Register 4) The TXHDR4 register contains the fourth byte of the Transmit Cell Header. (See TXHDR1.) Bit Default Name 7 0 TxHdr4[ TxHdr4[ TxHdr4[5] ...

Page 89

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x21—TXIDL2 (Transmit Idle Cell Header Control Register 2) The TXIDL2 register contains the second byte of the Transmit Idle Cell Header. (See TXIDL1.) Bit Default Name 7 0 TxIdl2[ TxIdl2[ ...

Page 90

Registers 4.2 Cell Transmit Control Registers 0x23—TXIDL4 (Transmit Idle Cell Header Control Register 4) The TXIDL4 register contains the fourth byte of the Transmit Idle Cell Header. (See TXIDL1.) Bit Default Name 7 0 TxIdl4[ TxIdl4[6] 5 ...

Page 91

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 4.3 Cell Receive Control Registers This section describes the control registers used for reception of traffic. 0x08—CVAL (Cell Validation Control Register) The CVAL register controls the validation of incoming cells to be received across ...

Page 92

Registers 4.3 Cell Receive Control Registers 0x24—RXHDR1 (Receive Cell Header Control Register 1) The RXHDR1 register contains the first byte of the Receive Cell Header. The header values direct ATM cells to the UTOPIA port incoming ATM ...

Page 93

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x26—RXHDR3 (Receive Cell Header Control Register 3) The RXHDR3 register contains the third byte of the Receive Cell Header. (See RXHDR1.) Bit Default Name 7 0 RxHdr3[ RxHdr3[ RxHdr3[5] 4 ...

Page 94

Registers 4.3 Cell Receive Control Registers 0x28—RXMSK1 (Receive Cell Mask Control Register 1) The RXMSK1 register contains the first byte of the Receive Cell Mask. It modifies the ATM cell screen in the Receive Cell Header Register. Setting a ...

Page 95

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x2A—RXMSK3 (Receive Cell Mask Control Register 3) The RXMSK3 register contains the third byte of the Receive Cell Mask. (See RXMSK1.) Bit Default Name 7 1 RxMsk3[ RxMsk3[ RxMsk3[5] 4 ...

Page 96

Registers 4.3 Cell Receive Control Registers 0x2C—RXIDL1 (Receive Idle Cell Header Control Register 1) The RXIDL1 register contains the first byte of the Receive Idle Cell Header. It defines ATM idle cells for the cell receiver. Idle cells are ...

Page 97

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x2E—RXIDL3 (Receive Idle Cell Header Control Register 3) The RXIDL3 register contains the third byte of the Receive Idle Cell Header. (See RXIDL1.) Bit Default Name 7 0 RxIdl3[ RxIdl3[ ...

Page 98

Registers 4.3 Cell Receive Control Registers 0x30—IDLMSK1 (Receive Idle Cell Mask Control Register 1) The IDLMSK1 register contains the first byte of the Receive Idle Cell Mask. It modifies the ATM cell screen in the RXIDL1 register. Setting a ...

Page 99

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x32—IDLMSK3 (Receive Idle Cell Mask Control Register 3) The IDLMSK3 register contains the third byte of the Receive Idle Cell Mask. (See RXMSKL1.) Bit Default Name 7 0 IdlMsk3[ IdlMsk3[ ...

Page 100

Registers 4.4 UTOPIA Control Registers 4.4 UTOPIA Control Registers This section describes the control registers for the UTOPIA block of the device. 0x0A—UTOP1 (UTOPIA Control Register 1) The UTOP1 register controls the mode of operation for the UTOPIA interface. ...

Page 101

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x0B—UTOP2 (UTOPIA Control Register 2) The UTOP2 register contains the multi-PHY address value for the device. Bit Default Name 7 0 Test Test UtopDis 4 0 MphyAddr[4] - ...

Page 102

Registers 4.5 SONET Overhead Transmit Control Registers 4.5 SONET Overhead Transmit Control Registers This section describes the control registers used for SONET Overhead transmission. 0x06—ERRINS (Error Insertion Control Register) The ERRINS register controls error insertion into various octets for ...

Page 103

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x07—ERRPAT (Error Pattern Control Register) The ERRPAT register provides the error pattern for the error insertion functions listed in the ERRINS register. Each bit in the error pattern register is XORed with the corresponding ...

Page 104

Registers 4.5 SONET Overhead Transmit Control Registers 0x68—TXSECBUF (Transmit Section Trace Circular Buffer) The TXSECBUF buffer, the J0 byte, is used to transmit repeatedly a 64-byte, fixed-length string so that a receiving terminal in a section can verify its ...

Page 105

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x0E—TXPTH (Transmit Path Overhead Control Register) The TXPTH register controls the transmission of various octets in the Path Overhead of the SONET frame. Bit Default Name 7 0 EnPthTr 6 0 DisB3 5 1 ...

Page 106

Registers 4.5 SONET Overhead Transmit Control Registers 0x10—TXK1 (Transmit K1 Overhead Control Register) (WAN Only) The TXK1 register controls the K1 byte in the transport overhead. The K1 and K2 bytes are allocated for Automatic Protection Switching (APS) signaling ...

Page 107

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x12—TXS1 (Transmit S1 Overhead Control Register) (WAN Only) The TXS1 register controls the S1 byte in the transport overhead. This byte is allocated for transporting synchronization status messages. This byte is defined only for ...

Page 108

Registers 4.6 SONET Overhead Receive Control Registers 4.6 SONET Overhead Receive Control Registers This section describes the control registers used for SONET Overhead reception. 0x6A—RXSECBUF (Receive Section Trace Circular Buffer) The RXSECBUF buffer, the J0 byte, is used to ...

Page 109

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x09—APSTHRESH (APS Threshold Control Register) (WAN Only) The APSTHRESH register sets the threshold value for Signal Fail and Signal Degrade Alarm generation. Bits 7-4 are the signal fail threshold exponent (default = 10 -6 ...

Page 110

Registers 4.6 SONET Overhead Receive Control Registers 0x15—RXK2 (Receive K2 Overhead Status Register) (WAN Only) The RXK2 register controls the K2 byte in the transport overhead. The K1 byte and bits 0-5 of the K2 byte are allocated for ...

Page 111

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x18—RXC2 (Receive C2 Overhead Status Register) The RXC2 register provides C2 overhead status. This byte is allocated to identify the construction and content of the STS-level SPE, and for STS Path Defect Indication (PDI-P). ...

Page 112

Registers 4.7 Status and Interrupt Registers 4.7 Status and Interrupt Registers These registers contain status and interrupt information. 0x34—ENSUMINT (Summary Interrupt Mask Control Register) The ENSUMINT register determines which of the interrupts listed in register 0x3C (SUMINT) are observed ...

Page 113

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x35—ENSEC (Receive Section Interrupt Mask Control Register) The ENSEC register controls which of the interrupts listed in the SecInt register (0x3D) appear on the MInt* pin (pin 6), provided that EnSecInt (bit 7) in ...

Page 114

Registers 4.7 Status and Interrupt Registers 0x37—ENPTH (Receive Path Interrupt Mask Control Register) The ENPTH register controls which of the interrupts listed in the PthInt register (0x3F) appear on the MInt* pin (pin 6), provided that EnPthInt (bit 5) ...

Page 115

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x38—ENCELLT (Transmit Cell Interrupt Mask Control Register) The ENCELLT register controls which of the interrupts listed in the TxCellInt register (0x40) appear on the MInt* pin (pin 6), provided that EnTxCellInt (bit 0) in ...

Page 116

Registers 4.7 Status and Interrupt Registers 0x39—ENCELLR (Receive Cell Interrupt Mask Control Register) The ENCELLR register controls which of the interrupts listed in the RxCellInt register (0x41) appear on the MInt* pin (pin 6), provided that EnRxCellInt (bit 1) ...

Page 117

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x3C—SUMINT (Summary Interrupt Indication Status Register) The SUMINT register indicates data link interrupts, one-second interrupts, and additional summary interrupts. Bit Default Name 7 x (2) SecInt 6 x (2) LinInt 5 x (2) PthInt ...

Page 118

Registers 4.7 Status and Interrupt Registers 0x3D—SECINT (Receive Section Interrupt Indication Status Register) The SECINT register indicates that a change of status has occurred within its affiliated status signals. Bit Default Name 7 x (1) SigDetInt 6 x (1) ...

Page 119

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x3F—PTHINT (Receive Path Interrupt Indication Status Register) The PTHINT register indicates that a change of status has occurred within its affiliated status signals. Bit Default Name x (1) 7 AIS-PInt x (1) 6 RDI-PInt ...

Page 120

Registers 4.7 Status and Interrupt Registers 0x40—TXCELLINT (Transmit Cell Interrupt Indication Status Register) The TXCELLINT register indicates that a change of status has occurred within its affiliated status signals. Bit Default Name 7 x (1) ParErrInt 6 x (1) ...

Page 121

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x45—RXSEC (Receive Section Overhead Status Register) The RXSEC register provides section overhead status. Bit Default Name 7 x (1) SigDet 6 x (1) LOL 5 x (1) LOS 4 x (1) OOF 3 x ...

Page 122

Registers 4.7 Status and Interrupt Registers 0x47—RXPTH (Receive Path Overhead Status Register) The RXPTH register contains status information for the receiver Path Overhead. Bit Default Name 7 x (1) AIS (1) RDI (2) B3Err 4 ...

Page 123

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x48—TXCELL (Transmit Cell Status Register) The TXCELL register contains status for the cell transmitter and the UTOPIA interface. Bit Default Name 7 x (1) ParErr 6 x (1) SOCErr 5 x (1) TxOvfl 4 ...

Page 124

Registers 4.8 Counters 4.8 Counters This section describes the RS825x’s 12 counters. When the counters fill, they saturate and do not roll over. The counts have been sized such that they will not saturate within a one-second interval. Therefore, ...

Page 125

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x4E—UNCCNT (Uncorrected HEC Error Counter) The UNCCNT counter tracks the number of uncorrected HEC errors. Bit Default Name 7 x UncCnt[ UncCnt[ UncCnt[ UncCnt[ UncCnt[3] 2 ...

Page 126

Registers 4.8 Counters 0x50—B2CNTL (Line BIP Error Counter [Low Byte]) The B2CNTL counter tracks the number of Line BIP errors. Bit Default Name 7 x B2Cnt[ B2Cnt[ B2Cnt[ B2Cnt[ B2Cnt[3] 2 ...

Page 127

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x52—B2CNTH (Line BIP Error Counter [High Byte]) The B2CNTH counter tracks the number of Line BIP errors. Bit Default Name 7 0 — — — — ...

Page 128

Registers 4.8 Counters 0x55—B1CNTH (Section BIP Error Counter [High Byte]) The B1CNTH counter tracks the number of Section BIP errors. Bit Default Name 7 x B1Cnt[15 B1Cnt[14 B1Cnt[13 B1Cnt[12 B1Cnt[11] 2 ...

Page 129

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x57—B3CNTH (Path BIP Error Counter [High Byte]) The B3CNTH counter tracks the number of Path BIP errors. Bit Default Name 7 x B3Cnt[15 B3Cnt[14 B3Cnt[13 B3Cnt[12 ...

Page 130

Registers 4.8 Counters 0x59—LFCNTM (Line FEBE Error Counter [Mid Byte]) The LFCNTM counter tracks the number of Line FEBE errors. Bit Default Name 7 x LFCnt[15 LFCnt[14 LFCnt[13 LFCnt[12 LFCnt[11] 2 ...

Page 131

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x5C—PFCNTL (Path FEBE Error Counter [Low Byte]) The PFCNTL counter tracks the number of Path FEBE errors. Bit Default Name 7 x PFCnt[ PFCnt[ PFCnt[ PFCnt[ ...

Page 132

Registers 4.8 Counters 0x5E—NONCNTL (Non-Matching Cell Counter [Low Byte]) The NONCNTL counter tracks the number of non-matching cells. Bit Default Name 7 x NonCnt[ NonCnt[ NonCnt[ NonCnt[ NonCnt[ NonCnt[2] ...

Page 133

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x60—TXCNTL (Transmitted Cell Counter [Low Byte]) The TXCNTL counter tracks the number of transmitted cells. Bit Default Name 7 x TxCnt[ TxCnt[ TxCnt[ TxCnt[ TxCnt[3] 2 ...

Page 134

Registers 4.8 Counters 0x62—TXCNTH (Transmitted Cell Counter [High Byte]) The TXCNTH counter tracks the number of transmitted cells. Bit Default Name 7 0 — — — — — TxCnt[18] ...

Page 135

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 0x65—RXCNTM (Received Cell Counter [Mid Byte]) The RXCNTM register tracks the number of received cells. Bit Default Name 7 x RxCnt[15 RxCnt[14 RxCnt[13 RxCnt[12 RxCnt[11] 2 ...

Page 136

Registers 4.8 Counters 4-60 ATM Physical Interface Devices—ATM PHY Preliminary N825xDSA RS8250/1/2/3/4/5 ...

Page 137

Electrical and Mechanical Specifications \ This chapter describes the electrical and mechanical aspects of the RS8251. Included are timing diagrams, absolute maximum ratings, DC characteristics and mechanical drawings. 5.1 Timing Specifications This section provides timing diagrams and descriptions ...

Page 138

Electrical and Mechanical Specifications 5.1 Timing Specifications Table 5-1. Timing Diagram Nomenclature ( Symbol Timing Relationship t Pulse Width pw t Pulse Width High pwh t Pulse Width Low pwl t Setup Time s t Setup High ...

Page 139

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table 5-1. Timing Diagram Nomenclature ( Symbol Timing Relationship t Hold Low Time hl t Propagation Delay pd t Propagation Delay - High-to-Low pdhl t Propagation Delay - Low-to-High pdlh t Enable ...

Page 140

Electrical and Mechanical Specifications 5.1 Timing Specifications Table 5-1. Timing Diagram Nomenclature ( Symbol Timing Relationship t Disable Time - High Disable dishz t Disable Time - Low Disable dislz t Recovery Time rec t Period per ...

Page 141

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Figure 5-2 shows how output waveforms are defined. Figure 5-2. Output Waveform 5.1.1 Microprocessor Interface Timing Tables 5-2 through 5-8 and Figures 5-3 through 5-8 display the timing requirements and characteristics of the microprocessor ...

Page 142

Electrical and Mechanical Specifications 5.1 Timing Specifications Table 5-2. Synchronous Mode, Read Timing Table Label t Pulse Width High, MClk pwh t Pulse Width Low, MClk pwl t Period, MClk per t Setup Low, MCs* to the rising edge ...

Page 143

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Figure 5-4. Synchronous Mode, Write Timing Diagram t sl1 MCs* t sh2 MW/R* MAs MAddr[6: MData[7: pwh pwl MClk MSyncMode (high) MCs* and MW/R* must not change state ...

Page 144

Electrical and Mechanical Specifications 5.1 Timing Specifications Table 5-3. Synchronous Mode, Write Timing Table Label t Setup Low, MAs* to the rising edge of MClk sl3 t Hold Low, MAs* from the rising edge of MClk hl3 t Setup ...

Page 145

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table 5-4. Asynchronous Mode, Read Timing Table (High-Performance Access Time) Label t Pulse Width Low, (MCs* + MRd*) pwl t Pulse Width High, (MCs* +MRd*) pwh t Setup, MAddr[6:0] to the falling edge of ...

Page 146

Electrical and Mechanical Specifications 5.1 Timing Specifications Figure 5-7. Asynchronous Mode, Read Timing Diagram (Low-Power Access Time MAddr[6:0] MCs* + MRd MData[7:0] MInt* MWr* (High) MAcsSel (Low) MSyncMode (Low) Table 5-6. Asynchronous Mode, Read Timing ...

Page 147

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Figure 5-8. Asynchronous Mode, Write Timing Diagram (Low-Power Access Time MAddr[6: MData[7:0] MCs* + MWr* MRd* (High) (Low) MAcsSel MSyncMode (Low) Table 5-7. Asynchronous Mode, Write Timing Table (Low-Power Access ...

Page 148

Electrical and Mechanical Specifications 5.1 Timing Specifications Figure 5-9. Transmit UTOPIA Interface Timing Diagram UTxSOC UTxEnb* UTxAddr[4:0] UTxData[15:0] UTxPrty UTxClAv UTxClk Table 5-8. Transmit UTOPIA Interface Timing Table ( Label t Setup, UTxSOC to the rising edge ...

Page 149

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table 5-8. Transmit UTOPIA Interface Timing Table ( Label t Enable, UTxClAv from the rising edge of UTxClk en t Propagation Delay, UTxClAv from the rising edge of UTxClk pd t Disable, ...

Page 150

Electrical and Mechanical Specifications 5.1 Timing Specifications Table 5-9. Receive UTOPIA Interface Timing Table Label t Setup, URxEnb* to the rising edge of URxClk s1 t Setup, URxAddr[4:0] to the rising edge of URxClk s2 t Hold, URxEnb* from ...

Page 151

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 5.1.4 JTAG Interface Timing Figure 5-11 and Table 5-10 show the timing requirements and characteristics of the JTAG interface. Figure 5-11. JTAG Timing Diagram TDO TDI TMS t t rec TCK TRST* Table 5-10. ...

Page 152

Electrical and Mechanical Specifications 5.1 Timing Specifications 5.1.5 One-second Interface Timing Table 5-11 and Figure 5-12 show the timing requirements and characteristics of the One-second interface. These output values are measured into load. Figure 5-12. One-Second ...

Page 153

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 5.2 Absolute Maximum Ratings The absolute maximum ratings listed below are the maximum stresses that the device can tolerate without risking permanent damage. These ratings are not typical of normal operation of the device. ...

Page 154

Electrical and Mechanical Specifications 5.3 DC Characteristics 5.3 DC Characteristics Table 5-13 describes the DC characteristics of the RS8251. Table 5-13. DC Characteristics Parameter Input Low Voltage (VIL) 5V-Tolerant TTL 5V-Tolerant HYS Input High Voltage (VIH) 5V-Tolerant TTL 5V-Tolerant ...

Page 155

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY 5.3.1 PECL - Input The PECL input DC characteristics are shown in Table 5-14. Table 5-14. PECL-Input DC Characteristics Symbol Parameter V Mid-point of V and V ref Input Voltage (high ...

Page 156

Electrical and Mechanical Specifications 5.4 Mechanical Drawing 5.4 Mechanical Drawing The RS8251 is a 128-pin TQFP. A mechanical drawing of the device is provided in Figure 5-13. Figure 5-13. RS8251 Mechanical Drawing PIN 1 REF ...

Page 157

A Appendix A: RS8252/3 Dual PHY Device This appendix describes the RS8252/3 Dual PHY and how it differs from the RS8251 PHY. A.1 RS8252/3 Pinout and Pin Descriptions Figure A pinout diagram for the RS8253 ATM Transmitter/Receiver. It ...

Page 158

Appendix A : RS8252/3 Dual PHY Device A.1 RS8252/3 Pinout and Pin Descriptions Figure A-1. RS8252/3 Pinout Diagram (Top View, Left Side MAs*,MWr OneSecin NC VGG 2 NC MSyncMode MCs Reset* ...

Page 159

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Appendix A : RS8252/3 Dual PHY Device A.1 RS8252/3 Pinout and Pin Descriptions Preliminary N825xDSA A-3 ...

Page 160

Appendix A : RS8252/3 Dual PHY Device A.1 RS8252/3 Pinout and Pin Descriptions Figure A-2. RS8252/3 Pinout Diagram (Top View, Right Side Mint*(a) TxDL(a) RxFrameRef(a) TCK StatOut[6](a) TxFrameRef(a) OneSecOut(a) 8khzIn URxData[8] URxData[7] URxAddr[0] URxData[6] URxData[14] URxData[10] ...

Page 161

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Pin names and numbers are listed in Table A-1. An asterisk(*) following a pin label indicates that the pin logic level is active low. Table A-1. RS8252/3 Pin Definitions (1 of 13) Pin Label ...

Page 162

Appendix A : RS8252/3 Dual PHY Device A.1 RS8252/3 Pinout and Pin Descriptions Table A-1. RS8252/3 Pin Definitions (2 of 13) Pin Label Signal Name LTxClkO+ Line Transmit (a) Clock Output (b) Positive Polarity (PHY a, b) LTxData- Line Transmit ...

Page 163

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table A-1. RS8252/3 Pin Definitions (3 of 13) Pin Label Signal Name MClk, MAcsSel Microprocessor Clock, Access Time Select MSyncMode Microprocessor Synchronous/Asy nchronous Bus Mode Select MCs* Microprocessor Chip Select MW/R*, MRd* Microprocessor Write/Read, ...

Page 164

Appendix A : RS8252/3 Dual PHY Device A.1 RS8252/3 Pinout and Pin Descriptions Table A-1. RS8252/3 Pin Definitions (4 of 13) Pin Label Signal Name MAs*,MWr* Microprocessor Address Strobe, Write Control MAddr[8] Microprocessor Address Bus MAddr[7] MAddr[6] MAddr[5] MAddr[4] MAddr[3] ...

Page 165

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table A-1. RS8252/3 Pin Definitions (5 of 13) Pin Label Signal Name TRST* Test Reset TCK Test Clock TMS Test Mode Select TDI(a) Test Data Input (PHY a) TDO(b) Test Data Output (PHY b) ...

Page 166

Appendix A : RS8252/3 Dual PHY Device A.1 RS8252/3 Pinout and Pin Descriptions Table A-1. RS8252/3 Pin Definitions (6 of 13) Pin Label Signal Name StatOut[7] Status (a) Outputs[7:0] (b) (PHY a, b) StatOut[6] (a) (b) StatOut[5] (a) (b) StatOut[4] ...

Page 167

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table A-1. RS8252/3 Pin Definitions (7 of 13) Pin Label Signal Name UTxClk UTOPIA Transmit Clock UTxEnb* UTOPIA Transmit Enable UTxAddr[0] LSB UTxAddr[1] UTOPIA Transmit UTxAddr[2] Address UTxAddr[3] UTxAddr[4] MSB UTxData[0] UTOPIA Transmit Data ...

Page 168

Appendix A : RS8252/3 Dual PHY Device A.1 RS8252/3 Pinout and Pin Descriptions Table A-1. RS8252/3 Pin Definitions (8 of 13) Pin Label Signal Name UTxSOC UTOPIA Transmit Start of Cell UTxClAv UTOPIA Transmit (a) Cell Available (b) (PHY a, ...

Page 169

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table A-1. RS8252/3 Pin Definitions (9 of 13) Pin Label Signal Name URxData[0] UTOPIA Receive Data Bus URxData[1] URxData[2] URxData[3] URxData[4] RxData[5] URxData[6] URxData[7] URxData[8] URxData[9] URxData[10] URxData[11] URxData[12] URxData[13] URxData[14] URxData[15] URxPrty UTOPIA ...

Page 170

Appendix A : RS8252/3 Dual PHY Device A.1 RS8252/3 Pinout and Pin Descriptions Table A-1. RS8252/3 Pin Definitions (10 of 13) Pin Label Signal Name URxClAv UTOPIA Receive (a) Cell Available (b) (PHY a, b) A-14 ATM Physical Interface Devices—ATM ...

Page 171

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table A-1. RS8252/3 Pin Definitions (11 of 13) Pin Label Signal Name PWR Supply Voltage Analog PWR Analog Supply Voltage Appendix A : RS8252/3 Dual PHY Device A.1 RS8252/3 Pinout and Pin Descriptions No. ...

Page 172

Appendix A : RS8252/3 Dual PHY Device A.1 RS8252/3 Pinout and Pin Descriptions Table A-1. RS8252/3 Pin Definitions (12 of 12) Pin Label Signal Name GND Ground Analog GND Analog Ground V Electrostatic GG Discharge (ESD) Supply Voltage 1. RS8252/3 ...

Page 173

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY A.2 RS8252/3 Register Map There are seven primary address pins, Addr[6:0], which designate the 128 address locations on each port of the device. To accommodate multiple PHY parts; i.e., RS8252/3/4/5, a total of nine ...

Page 174

Appendix A : RS8252/3 Dual PHY Device A.3 RS8252/3 Electrical and Mechanical Description A.3.1 RS8252/3 Mechanical Drawing The RS8252/3 mechanical drawing is shown in Figure A-3. Figure A-3. 256-Pin Ball Gate Array Package (BGA), for RS8252/3 35.000 ± 30.000 .050 ...

Page 175

B Appendix B: RS8254/5 Quad PHY Device This appendix describes the RS8254/5 Quad PHY and how it differs from the RS8251 PHY. B.1 RS8254/5 Pinout and Pin Descriptions Figure B pinout diagram for the RS8254/5 ATM Transmitter/Receiver. It ...

Page 176

Appendix B : RS8254/5 Quad PHY Device B.1 RS8254/5 Pinout and Pin Descriptions Figure B-1. RS8254/5 Pinout Diagram (top view, left side MAs*,MWr OneSecin MInt*(d) VGG 2 NC MSyncMode MCs Reset* ...

Page 177

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Appendix B : RS8254/5 Quad PHY Device B.1 RS8254/5 Pinout and Pin Descriptions Preliminary N825xDSA B-3 ...

Page 178

Appendix B : RS8254/5 Quad PHY Device B.1 RS8254/5 Pinout and Pin Descriptions Figure B-2. RS8254/5 Pinout Diagram (Top View, Right Side Mint*(a) TxDL(a) RxFrameRef(a) TCK StatOut[6](a) TxFrameRef(a) OneSecOut(a) 8khzIn URxData[8] URxData[7] URxAddr[0] URxData[6] URxData[14] URxData[10] ...

Page 179

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Pin names and numbers are listed in Table B-1. An asterisk (*) following a pin label indicates that the pin logic level is active low. Table B-1. RS8254/5 Pin Definitions (1 of 13) Pin ...

Page 180

Appendix B : RS8254/5 Quad PHY Device B.1 RS8254/5 Pinout and Pin Descriptions Table B-1. RS8254/5 Pin Definitions (2 of 13) Pin Label Signal Name LTxClkI- Line Transmit Clock Input Negative Polarity LTxClkI+ Line Transmit Clock Input Positive Polarity LTxClkO- ...

Page 181

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table B-1. RS8254/5 Pin Definitions (3 of 13) Pin Label Signal Name LTxClkO+ Line Transmit (a) Clock Output (b) Positive Polarity (c) (PHY (d) LTxData- Line Transmit (a) Output Negative ...

Page 182

Appendix B : RS8254/5 Quad PHY Device B.1 RS8254/5 Pinout and Pin Descriptions Table B-1. RS8254/5 Pin Definitions (4 of 13) Pin Label Signal Name MClk, Microprocessor MAcsSel Clock, Access Time Select MSyncMode Microprocessor Synchronous/Asy nchronous Bus Mode Select MCs* ...

Page 183

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table B-1. RS8254/5 Pin Definitions (5 of 13) Pin Label Signal Name MAs*,MWr* Microprocessor Address Strobe, Write Control MAddr[8] Microprocessor Address Bus MAddr[7] MAddr[6] MAddr[5] MAddr[4] MAddr[3] MAddr[2] MAddr[1] MAddr[0] MData[7] Microprocessor Data Bus ...

Page 184

Appendix B : RS8254/5 Quad PHY Device B.1 RS8254/5 Pinout and Pin Descriptions Table B-1. RS8254/5 Pin Definitions (6 of 13) Pin Label Signal Name TRST* Test Reset TCK Test Clock TMS Test Mode Select TDI(a) Test Data Input (PHY ...

Page 185

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table B-1. RS8254/5 Pin Definitions (7 of 13) Pin Label Signal Name StatOut[7] Status (a) Outputs[7:0] (b) (PHY (c) (d) StatOut[6] (a) (b) (c) (d) StatOut[5] (a) (b) (c) (d) ...

Page 186

Appendix B : RS8254/5 Quad PHY Device B.1 RS8254/5 Pinout and Pin Descriptions Table B-1. RS8254/5 Pin Definitions (8 of 13) Pin Label Signal Name UTxClk UTOPIA Transmit Clock UTxEnb* UTOPIA Transmit Enable UTxAddr[0] LSB UTxAddr[1] UTOPIA Transmit UTxAddr[2] Address ...

Page 187

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table B-1. RS8254/5 Pin Definitions (9 of 13) Pin Label Signal Name UTxSOC UTOPIA Transmit Start of Cell UTxClAv UTOPIA Transmit (a) Cell Available (b) (PHY (c) d) (d) URxClk UTOPIA ...

Page 188

Appendix B : RS8254/5 Quad PHY Device B.1 RS8254/5 Pinout and Pin Descriptions Table B-1. RS8254/5 Pin Definitions (10 of 13) Pin Label Signal Name URxData[0] UTOPIA Receive Data Bus URxData[1] URxData[2] URxData[3] URxData[4] URxData[5] URxData[6] URxData[7] URxData[8] URxData[9] URxData[10] ...

Page 189

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table B-1. RS8254/5 Pin Definitions (11 of 13) Pin Label Signal Name URxClAv UTOPIA Receive (a) Cell Available (b) (PHY (c) d) (d) Appendix B : RS8254/5 Quad PHY Device B.1 ...

Page 190

Appendix B : RS8254/5 Quad PHY Device B.1 RS8254/5 Pinout and Pin Descriptions Table B-1. RS8254/5 Pin Definitions (12 of 13) Pin Label Signal Name PWR Supply Voltage Analog PWR Analog Supply Voltage B-16 ATM Physical Interface Devices—ATM PHY No. ...

Page 191

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table B-1. RS8254/5 Pin Definitions (13 of 13) Pin Label Signal Name GND Ground Analog GND Analog Ground V Electrostatic GG Discharge (ESD) Supply Voltage Notes: (1) RS8254/5 defaults to UTOPIA Level 2 when ...

Page 192

Appendix B : RS8254/5 Quad PHY Device B.3 RS8254/5 Electrical and Mechanical Description B.2 RS8254/5 Register Map There are seven primary address pins, Addr[6:0], which designate the 128 address locations on each port of the device. To accommodate multiple PHY ...

Page 193

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Figure B-3. 256-Pin Ball Gate Array Package (BGA) for the RS8254/5 35.000±.100 30.000±.050 7 PIN A1 TRIANGLE (UNDERSIDE) 1.70 R TYP 4 PL OPTIONAL TOP VIEW 45° CHAMFER TYP ...

Page 194

Appendix B : RS8254/5 Quad PHY Device B.3 RS8254/5 Electrical and Mechanical Description B-20 ATM Physical Interface Devices—ATM PHY Preliminary N825xDSA RS8250/1/2/3/4/5 ...

Page 195

C Appendix C : RS8250 PHY Device This appendix describes the RS8250 PHY and how it differs from the RS8251 PHY. C.1 RS8250 Pinout and Pin Descriptions Figure C pinout diagram for the RS8250 ATM Transmitter/Receiver ...

Page 196

Appendix C : RS8250 PHY Device C.1 RS8250 Pinout and Pin Descriptions Figure C-1. RS8250 Pinout Diagram (Top View, Left Side StatOut[1] StatOut[ StatOut[4] URxAddr[1] StatOut[0] StatOut[5] B MInt* StatOut[2] MW/R*,MRd* StatOut[6] C MCs* ...

Page 197

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table C-1. RS8250 Pin Definitions (1 of 11) Pin Label Signal Name Reset* Device Reset OneSecIn One-Second Strobe OneSecOut One-Second Output TxFrameRef Transmit Frame Clock RxFrameRef Receive Frame Clock 8kHzIn 8 kHz Reference Clock ...

Page 198

Appendix C : RS8250 PHY Device C.1 RS8250 Pinout and Pin Descriptions Table C-1. RS8250 Pin Definitions (2 of 11) Pin Label Signal Name LTxData+ Line Transmit Output Positive Polarity LRxClk- Line Receive Clock Negative LRxClk+ Line Receive Clock Positive ...

Page 199

RS8250/1/2/3/4/5 ATM Physical Interface Devices—ATM PHY Table C-1. RS8250 Pin Definitions (3 of 11) Pin Label Signal Name MClk, Microprocessor MAcsSel Clock, Access Time Select MSyncMode Microprocessor Synchronous/As ynchronous Bus Mode Select MCs* Microprocessor Chip Select MW/R*, Microprocessor MRd* Write/Read, ...

Page 200

Appendix C : RS8250 PHY Device C.1 RS8250 Pinout and Pin Descriptions Table C-1. RS8250 Pin Definitions (4 of 11) Pin Label Signal Name MAs*,MWr* Microprocessor Address Strobe, Write Control MAddr[8] Microprocessor Address Bus MAddr[7] MAddr[6] MAddr[5] MAddr[4] MAddr[3] MAddr[2] ...

Related keywords