CX28395 Conexant Systems, Inc., CX28395 Datasheet

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CX28395

Manufacturer Part Number
CX28395
Description
Manufacturer
Conexant Systems, Inc.
Datasheet

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CX28394/28395/28398
Quad/x16/Octal—T1/E1/J1 Framers
The CX28394/28395/28398 is a family of multiple framers for T1/E1/J1 and Integrated
Service Digital Network (ISDN) primary rate interfaces operating at 1.544 Mbps or 2.048
Mbps. All framers are totally independent, and each combines a sophisticated framing
synchronizer and transmit/receive slip buffers. Operations are controlled through a
series of memory-mapped registers accessible via a parallel microprocessor port.
Extensive register support is provided for alarm and error monitoring, signaling
supervision (including ISDN D-channel/SS7 process), per-channel trunk conditioning,
and Facility Data Link (FDL) maintenance. A flexible serial Time Division Multiplexed
(TDM) system interface that supports bus rates from 1.536 to 8.192 MHz is featured.
Extensive test and diagnostic functions include a full set of loopbacks, Pseudo Random
Bit Sequence (PRBS) test pattern generation, Bit Error Rate (BER) meter, and forced
error insertion.
Functional Block Diagram
. .
.
Data Sheet
* CX28394 and CX28398 only.
Framer #1
Dual Rail or
Dual Rail or
Framer #N
Receive
Receive
NRZ
NRZ
Decode
Encode
Test Port
ZCS*
ZCS*
JTAG
Control/Status
Processor Bus
Motorola/Intel
Overhead
Receive
Insertion
Framer
Registers
T1/E1
Data Link Controllers
External Data Link
Transmit
Framer
T1/E1
Buffer
Buffer
Slip
Slip
RX
TX
DL1+DL2
DL3*
CX28394 - 4 Frames
CX28398 - 8 Frames
CX28395 - 16 Frames
Framer #N
Receive
System
Bus
Transmit
System
Bus
Distinguishing Features
• Up to 16 T1/E1/J1 Framers in one
• Extensive support of various
• T1: SF, ESF, SLC
• E1: PCM-30, G.704, G.706, G.732,
• Extracts and inserts signaling bits
• Dual HDLC controllers per framer for
• Two-frame transmit and receive PCM
• Separate or multiplexed system bus
• Parallel 8-bit microprocessor port
• BERT generation and counting
• B8ZS/HDB3/Bit 7 zero suppression
• Operates from a single +3.3 Vdc
• Low-power CMOS technology
Applications
• Multiline T1/E1 Channel Service
• Digital Access Cross-Connect
• T1/E1 Multiplexer (MUX)
• PBXs and PCM channel bank
• ISDN Primary Rate Access (PRA)
• Frame Relay Switches and Access
• SONET/SDH add/drop multiplexers
• T3/E3 channelized access
package
protocols
TTC JT(J1)
ISDN primary rate (ETS300 011,
INS 500)
data link and LAPD/SS7 signaling
slip buffers
interfaces
supports Intel or Motorola buses
(CX28394 and CX28398 only)
Unit/Data Service Unit (CSU/DSU)
System (DACS)
Devices (FRADS)
concentrators
5% power supply
®
96, T1DM,
June 2000
100054E

Related parts for CX28395

CX28395 Summary of contents

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... T1/E1 Transmit Framer Data Link Controllers DL1+DL2 External Data Link DL3* Framer #N CX28394 - 4 Frames CX28398 - 8 Frames CX28395 - 16 Frames Distinguishing Features • T1/E1/J1 Framers in one package • Extensive support of various protocols ® • T1: SF, ESF, SLC 96, T1DM, TTC JT(J1) • E1: PCM-30, G.704, G.706, G.732, ...

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... Conexant products for use in such applications their own risk and agree to fully indemnify Conexant for any damages resulting from such improper use or sale. The following are trademarks of Conexant Systems, Inc.: Conexant™, the Conexant C symbol, and “What’s Next in Communications Technologies”™. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners. For additional disclaimer information, please consult Conexant’ ...

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... Local PCM Highways 32 at 1536 kbps 8192 kbps) Package 4 128-pin TQFP 8 208-pin PQFP 8 272-pin BGA 16 318-pin BGA 16 318-pin BGA 8 208-pin CABGA CX28398/CX28380 Evaluation Module Conexant CX28395 ( x16 T1/E1 Framer) Operating Temperature – – – – – ...

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Detailed Feature Summary Frame Alignment • Framed formats: – Independent transmit and receive framing modes – T1: FT/SF/ESF/SLC/T1DM/TTC-JT(J1) – E1: FAS/MFAS/FAS+CAS/MFAS+CAS • Maximum Average Reframe Time (MART) less than 50 ms • Transmitter alignment modes: – Align to system bus ...

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Data Links • Two full-featured data link controllers (DL1 and DL2): – 64-octet transmit and receive FIFOs – HDLC Message Oriented Protocol (MOP) – Unformatted data transfer – Unformatted circular buffer – End of message/buffer interrupt – Near full/empty interrupts ...

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Conexant ...

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Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 2.2.5 Alarm Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 2.4.3 Sa-Byte Overwrite Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 3.5 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 3.10 Performance Monitoring Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 3.15 Data Link Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 140–15F—Transmit PCM Slip Buffer (TSLIP_LOn 31 3-112 160–17F—Transmit PCM Slip Buffer (TSLIP_HIn ...

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Table of Contents xiv CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Conexant 100054E ...

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... CX28395 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Figure 1-2. CX28394 128-pin TQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Figure 1-3. CX28395 318-pin BGA Pinout Diagram 1-5 Figure 1-4. CX28398 208-pin PQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Figure 1-5. CX28398 208-pin CABGA Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Figure 1-6 ...

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List of Figures Figure 2-28. Interrupt Generation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62 Table 2-9. CX28394 Device Identification JTAG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63 Table 2-10. CX28395 Device Identification JTAG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63 Table 2-11. CX28398 Device Identification JTAG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63 Table 3-1. Address Offset Map (CX28394 3-1 Table 3-2 ...

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List of Tables Table 3-23. Remote DS0 Channel Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... On the CX28394 and CX28398 devices, these signals appear on different pins depending on whether Multiplexed System Bus mode or Non-Multiplexed System Bus mode is selected. On the CX28395, they are available only in Multiplexed Bus mode. 100054E 1 ...

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... CX28380 Quad T1/E1 LIU. This interface allows the microprocessor to control and query the LIU status. This serial interface is not available on the CX28395. 1.1.4 Transmit/Receive Line Interface The CX28394 and CX28398 devices include line interfaces which can operate in either of two modes: bipolar NRZ or unipolar NRZ. In bipolar NRZ mode, receiver signals RPOSI, RNEGI, and RCKI are used ...

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... CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 1.2 Pin Assignments The CX28394 is packaged in a 128-pin Quad Flat Pack (TQFP). The CX28395 is packaged in a 318-pin Ball Grid Array (BGA) multi-chip module (MCM). The CX28398 has two package alternatives: a 208-pin Quad Flat Pack (MQFP) and a 272-pin BGA. Pinout diagrams are provided in Tables 1-1 lists all other pin assignments ...

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Product Description 1.2 Pin Assignments Figure 1-2. CX28394 128-pin TQFP Pinout Diagram TNEGO[4] / MSYNCO[ TCKI[4] 2 RCKI[4] 3 RPOSI[ ...

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... CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Figure 1-3. CX28395 318-pin BGA Pinout Diagram 100054E Top View Conexant 1.0 Product Description 1 ...

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Product Description 1.2 Pin Assignments Figure 1-4. CX28398 208-pin PQFP Pinout Diagram VGG 1 VSS 2 TSB3 / RSB3 TRST* 3 TMS 4 TDI 5 TDO 6 JTAG TCK 7 VDD 8 FSYNC[8] / TMSYNC[8] 9 TSBCKI[8] / TFSYNC[B] ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Figure 1-5. CX28398 208-pin CABGA Pinout Diagram 100054E ...

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Product Description 1.2 Pin Assignments Figure 1-6. CX28398 272-pin BGA Pinout Diagram ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 1-1. Pin Assignments (SBI1, SBI2, SBI3, SBI4 Pin Number 89 94 R12 V15 90 95 P11 W16 91 96 U14 Y17 92 97 T14 V16 93 98 R13 W17 — — — — ...

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Product Description 1.2 Pin Assignments Table 1-1. Pin Assignments (SBI1, SBI2, SBI3, SBI4 Pin Number 27 200 201 202 B5 B4 — — — — 30 203 ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 1-2. Pin Assignments (SBI5, SBI6, SBI7, SBI8 Pin Number — 81 U10 Y12 — W12 — V12 — 84 T10 Y13 — 85 R10 W13 — — — — ...

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Product Description 1.2 Pin Assignments Table 1-2. Pin Assignments (SBI5, SBI6, SBI7, SBI8 Pin Number — — — — — — — — — ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 1-3. Pin Assignments (SBI9, SBI10, SBI11, SBI12 Pin Number — — — — — — — — — — — — — — — — — — — — — — — — ...

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Product Description 1.2 Pin Assignments Table 1-3. Pin Assignments (SBI9, SBI10, SBI11, SBI12 Pin Number — — — — — — — — — — — — — — — — — — — — — ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 1-4. Pin Assignments (SBI13, SBI14, SBI15, SBI16 Pin Number — — — — — — — — — — — — — — — — — — — — — — — — ...

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Product Description 1.2 Pin Assignments Table 1-5. Pin Assignments ( — — — — — — — — — — — — — — — — — — — — — ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 1-5. Pin Assignments ( 119 — — — — — — — — 41 — — — — 45 — — ...

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Product Description 1.2 Pin Assignments Table 1-5. Pin Assignments ( — — — — — ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 1-5. Pin Assignments ( 100 101 102 103 — 104 107 105 106 108 109 110 112 115 113 114 116 117 118 120 123 121 122 124 125 126 127 ...

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Product Description 1.2 Pin Assignments Table 1-5. Pin Assignments ( 128 — — — — — — — — — — — — — — — — — — — — — ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 1-5. Pin Assignments ( — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — ...

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Product Description 1.2 Pin Assignments Table 1-5. Pin Assignments ( — — — — — — — — — — — — — — — — — — — — — — — — — — — ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 1-5. Pin Assignments ( — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — ...

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Product Description 1.2 Pin Assignments Table 1-5. Pin Assignments ( — — — — 1-24 Quad/x16/Octal—T1/E1/J1 Framers Pin Number — — D10 — NC — — D9 — NC — — D7 — NC — — D5 ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Figure 1-7. CX28394 Logic Diagram (Non-Multiplexed System Bus Mode) Hardware Reset I RST* System Clock I SYSCKI Processor Clock I MCLK Synchronous Bus mode I SYNCMD Motorola Bus mode I MOTO* Address Strobe I AS*(ALE*) Chip Select ...

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Product Description 1.2 Pin Assignments Figure 1-8. CX28394 Logic Diagram (Multiplexed System Bus Mode) Hardware Reset I RST* System Clock I SYSCKI Processor Clock I MCLK Synchronous Bus mode I SYNCMD Motorola Bus mode I MOTO* Address Strobe I ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Figure 1-9. CX28398 Logic Diagram (Non-Multiplexed System Bus Mode) Hardware Reset I RST* System Clock I SYSCKI Processor Clock I MCLK Synchronous Bus mode I SYNCMD Motorola Bus mode I MOTO* Address Strobe I AS*(ALE*) Chip Select ...

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Product Description 1.2 Pin Assignments Figure 1-10. CX28398 Logic Diagram (Multiplexed System Bus Mode) Hardware Reset I RST* System Clock I SYSCKI Processor Clock I MCLK Synchronous Bus mode I SYNCMD Motorola Bus mode I MOTO* Address Strobe I ...

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... CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Figure 1-11. CX28395 Logic Diagram (Non-Multiplexed System Bus Mode) Hardware Reset I RST* System Clock I SYSCKI Processor Clock I MCLK Synchronous Bus mode I SYNCMD Motorola Bus mode I MOTO* Address Strobe I AS*(ALE*) Chip Select 1 I CS1* Chip Select 2 I CS2* ...

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... Product Description 1.2 Pin Assignments Figure 1-12. CX28395 Logic Diagram (Multiplexed System Bus Mode) Hardware Reset I System Clock I Processor Clock I Synchronous Bus Mode I Motorola Bus Mode I Address Strobe I Chip Select 1 I Chip Select 2 I Data or Read Strobe I Read/Write or Write Strobe I Data or Multiplexed I/O Address/Data Bus ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 1-6. Hardware Signal Definitions ( Pin Label Signal Name RST* Hardware Reset SYSCKI System Clock MCLK Processor Clock SYNCMD Sync mode MOTO* Motorola Bus Mode A[10:0] Address Bus A[11:0] Address Bus AD[7:0] Data Bus ...

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Product Description 1.2 Pin Assignments Table 1-6. Hardware Signal Definitions ( Pin Label Signal Name CS* Chip Select DS*(RD*) Data Strobe or Read Strobe R/W*(WR*) Read/Write Direction or Write Strobe ONESEC One Second Timer ONESEC1 One Second ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 1-6. Hardware Signal Definitions ( Pin Label Signal Name SERDI Serial Data Input SERCKO Serial Clock SERDO Serial Data Output SERCS* Serial Chip Select SERCS1* Serial Chip SERCS2* Selects TCKI[4:1] TX Clock Input TCKI[8:1] ...

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Product Description 1.2 Pin Assignments Table 1-6. Hardware Signal Definitions ( Pin Label Signal Name TCKO[4:1] TX Clock Output TCKO[8:1] TCKO[16:1] TNRZO[4:1] TX Non Return TNRZO[8:1] to Zero Data TNRZO[16:1] MSYNCO[4:1] TX Multiframe MSYNCO[8:1] Sync MSYNCO[16:1] RCKI[4:1] ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 1-6. Hardware Signal Definitions ( Pin Label Signal Name TSBCKI[4:1] TSB Clock Input TSBCKI[8:1] TSBCKI[16:1] TSBCKI[A] Bused TSB Clock TSBCKI[B] Inputs TSBCKI[C] TSBCKI[D} TPCMI[4:1] TSB Data Input TPCMI[8:1] TPCMI[16:1] TPCMI[A] Bused TSB Data TPCMI[B] ...

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... Active high output pulse marks selective receive system 8 bus time slots as programmed by SBCn [addr 0E0-0FF]. 4,5,8 RINDO occurs on RSBCKI rising or falling edges as 5,8 selected by RPCM_NEG (see [RSBI; addr 0D1]). Only 5 available in Multiplexed System Bus mode on CX28395 5 (see [FCR; addr 080]). Conexant CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Definition 100054E ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 1-6. Hardware Signal Definitions ( Pin Label Signal Name RSIGO[4:1] RSB Signaling RSIGO[8:1] Output RSIGO[16:1] RFSYNC[4:1] RSB Frame Sync RFSYNC[8:1] RFSYNC[16:1] RFSYNC[A] Bused RSB RFSYNC[B] Frame Sync RFSYNC[C] RFSYNC[D] RMSYNC[4:1] RSB Multiframe RMSYNC[8:1] Sync ...

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Product Description 1.2 Pin Assignments Table 1-6. Hardware Signal Definitions ( Pin Label Signal Name TCK JTAG Clock TDI1, TDI2 JTAG Test Data Input TDI JTAG Test Data Input TMS JTAG Test mode Select TDO JTAG Test ...

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... Test Output TSTI[16:1] Test Input NOTE(S): ( CX28394 5 = CX28395 8 = CX28398 1. All RSB and TSB outputs can be placed in high-impedance state (see SBI_OE; addr 0D0 Input Output 3. PIO = Programmable I/O; controls located at address 018. 4. Multiple signal names show mutually exclusive pin functions. 100054E ...

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Product Description 1.2 Pin Assignments 1-40 CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Conexant 100054E ...

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Circuit Description 2.1 Functional Block Diagram Figures 2-1 and multiplexed system bus modes. To show the details of these circuits, individual block diagrams of the functions listed below have been created and are placed, along with descriptions, throughout this ...

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... ONESEC RST* (1) SERCS[1:0] SERCLK SERDO (1) TPOSO[1] SERI (1) TNEGO[1] TNRZO[1] TCK MSYNCO [1] TMS TDI TDO TRST* NOTE(S): (1) Not available on CX28395. 2-2 RDLO[1] RDLCKO[1] (1) (1) RSIG External DLINK Buffer PRBS/Inband LB DLINK2 Buffer RSIG DLINK1 Buffer Local Sa-Byte/BOP PDV Monitor RSLIP RZCS Buffer Decoder AIS ...

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... ONESEC RST* (1) SERCS[1:0] SERCLK SERDO (1) TPOSO[1] SERI (1) TNEGO[1] TNRZO[1] TCK MSYNCO [1] TMS TDI TDO TRST* NOTE(S): (1) Not available on CX28395. 100054E RDLO[1] RDLCKO[1] (1) (1) RSIG External DLINK Buffer PRBS/Inband LB DLINK2 Buffer RSIG DLINK1 Buffer Local Sa-Byte/BOP PDV Monitor RSLIP RZCS Buffer Decoder ...

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Circuit Description 2.2 Receiver 2.2 Receiver The Receiver (RCVR) inputs single rail NRZ data or decodes positive and negative rail NRZ data into single rail NRZ data. The RCVR, illustrated in Figure (RZCS) Decoder, In-Band Loopback Code Detector, Error ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 2.2.2 In-Band Loopback Code Detection The in-band loopback code detector circuitry detects receive data with in-band codes of configurable value and length. These codes can be used to request loopback of terminal equipment signals or other user ...

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Circuit Description 2.2 Receiver 2.2.3.1 Frame Bit Error The 12-bit Framing Bit Error Counter [FERR; addr 050 and 051] increments Counter every time a receive Ft, Fs, T1DM, FPS, or FAS error is detected. Fs (T1) and NFAS (E1) ...

Page 65

CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 2.2.4.2 MFAS Error When CRC4 framing is enabled, MERR is reported for the receive direction in the Error Interrupt Status register [ISR5; addr 006] and for the transmit direction in Pattern Interrupt Status [ISR0; addr 00B]. MERR ...

Page 66

Circuit Description 2.2 Receiver 2.2.5.1 Loss of Frame Receive Loss Of Frame (RLOF) is declared when the receive data stream does not meet the framing criteria specified in the Receiver Configuration register [RCR0; addr 040]. If the line rate ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 2.2.5.6 Multiframe YEL The criteria for Multiframe Yellow Alarm is described in Yellow Alarm Set/Clear ALM1, and the interrupt is available in ISR7. 2.2.5.7 Severely Errored A SEF is reported when the receive signal does not meet ...

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Circuit Description 2.2 Receiver 2.2.7 Receive Framing Two framers are in the receive data stream: an offline framer and an online frame status monitor. The offline framer recovers receive frame alignment; the online framer monitors frame alignment patterns and ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 2-1. Receive Framer Modes T1/E1N 100054E RFRAME[3:0] 0 000X 0 001X 0 010X 0 011X 0 100X 0 101X 0 110X 0 111X 1 0000 1 0001 1 0100 1 0101 1 0110 1 1000 1 ...

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Circuit Description 2.2 Receiver Table 2-2. Criteria for Loss/Recovery of Receive Framer Alignment Mode FAS Basic Frame Alignment (BFA) is recovered when the following search criteria are satisfied: • FAS pattern (0011011) is found in frame N. • Frame ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 2-2. Criteria for Loss/Recovery of Receive Framer Alignment Mode SF Superframe alignment is recovered when: • Terminal frame alignment is recovered, identifying Ft bits. • Depends on SF submode: If JYEL, only Ft bits are used, ...

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Circuit Description 2.2 Receiver The offline framer waits until the current search is complete (see [FSTAT; addr 017]) before checking for pending LOF reframe requests. If both online framers have pending reframe requests, the offline framer aligns to the ...

Page 73

... This gives the processor after the receive multiframe interrupt [RMF; addr 008] occurs to read any Sa-Byte buffer before the buffer content changes. 100054E Figure 2-4. DL3 signals are not provided on the CX28395. Therefore, DL3_TS must be written disable the DL3 transmitter and prevent transmit data corruption. Frame 2 Frame 3 ...

Page 74

Circuit Description 2.2 Receiver 2.2.10 Receive Data Link The RCVR contains two independent data link controllers (DL1 and DL2) and a Bit-Oriented Protocol (BOP) transceiver. DL1 and DL2 can be programmed to send and receive HDLC formatted messages in ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers The Receive Data Link FIFO #1 [RDL1; addr 0A8 bytes. The Receive FIFO buffer is formatted differently than the transmit FIFO buffer. The Receive buffer contains not only received messages, but also a status byte ...

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Circuit Description 2.2 Receiver Figure 2-5. Polled Receive Data Link Processing Wait N Milliseconds Message status contains number of message bytes (X) in FIFO. NOTE(S): 2-18 Receive Message Read Data Link Status If Yes FIFO EMPTY ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Figure 2-6. Interrupt-Driven Receive Data Link Processing Read Message Byte from FIFO and Discard Message status contains number of message bytes (X) in FIFO. NOTE(S): 100054E Interrupt Service Routine Interrupt Occurred Read Interrupt Status No Complete MSG ...

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Circuit Description 2.2 Receiver 2.2.10.2 RBOP Receiver The Receive Bit-Oriented Protocol (RBOP) receiver receives BOP messages, including the ESF Yellow Alarm, which consists of repeated 16-bit patterns with an embedded 6-bit codeword as shown in this example: The BOP ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 2.3 System Bus Each framer provides high-speed, transmit and receive serial TDM interfaces. These interfaces can be configured as non-multiplexed, individual system buses, or they can be multiplexed internally or externally to provide 2xE1 (4096 Mbps) and ...

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Circuit Description 2.3 System Bus 2.3.2 Externally Multiplexed Mode Externally Multiplexed mode allows any two, three, or four framers (in the same or different devices) to share a common high speed system bus (see The 4.096 and 8.192 MHz ...

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... A) and framers 5 through 8 form another (upper group or group B). The CX28395 supports four groups and D. The CX28394’s four framers are also grouped in the same manner. In this mode, system bus signals from all four framers are internally connected and the interface pin functions are redefined ...

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Circuit Description 2.3 System Bus Figure 2-8. Internally Multiplexed Configuration Examples Possible Internally Multiplexed Configurations 8.192 Mbps Framer 1 Two separte 8.192 Framer 2 Mbps buses is the typical application for Framer 3 Internally Multiplexed mode. Framer 4 8.192 ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Figure 2-9 are provided in configured to output on the rising or falling edge of RSBCKI (see the Receive System Bus Configuration register [RSB_CR; addr 0D1]). Figure 2-9. RSB Waveforms RSBCKI Frame ...

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Circuit Description 2.3 System Bus The 4.096 and 8.192 MHz bus modes contain multiple bus members ( which allow multiple T1/E1 signals to share the same system bus. This is done by interleaving the time slots ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers The RSB maps line rate time slots to system bus time slots. The 24 (DS1 (CEPT) line rate time slots can be mapped to 24, 32, 64, or 128 system bus time slots as listed ...

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Circuit Description 2.3 System Bus 2.3.4.1 Timebase The RSB timebase synchronizes RFSYNC, RMSYNC, and RINDO with the Receive System Bus Clock (RSBCKI). The RSBCK can be slaved to two different clock sources: Receive System Bus Clock Input (RSBCKI), or ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Figure 2-13. T1 Line to E1 System Bus Time Slot Mapping Frame RNRZ A RPCMO NOTE(S): ( unassigned time slots ( frame bit, frame ...

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Circuit Description 2.3 System Bus 64-Bit Elastic In 64-bit Elastic mode, the slip buffer total depth is 64 bits, and the initial throughput delay is 32 bits, one-half of the total depth. Similar to Normal mode, Elastic mode allows ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 2.3.4.4 Signaling Stack The Receive Signaling Stack (RSTACK) allows the processor to quickly extract signaling changes without polling every channel. RSTACK is activated on a per-channel basis by setting the Received Signaling Stack (SIG_STK) control bit in ...

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Circuit Description 2.3 System Bus 2.3.5 Transmit System Bus The Transmit System Bus (TSB) consists of a timebase, slip buffer, signaling buffer, and transmit framer between the XMTR and the system bus. Figure 2-15. TSB Interface Block Diagram From ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Refer to definitions are provided in outputs can be configured to input data on the rising or falling edge of TSBCKI (see the Transmit System Bus Configuration register [TSB_CR; addr 0D4]. Figure 2-16. Transmit System Bus Waveforms ...

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Circuit Description 2.3 System Bus The 4.096 and 8.192 MHz bus modes contain multiple bus members ( and D) of which one bus member is selected by the SBI [3:0] bits in the System Bus Interface Configuration ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 2.3.5.1 Timebase The TSB timebase synchronizes TPCMI, TFSYNC, TMSYNC, and TINDO with the Transmit System Bus Clock (TSBCK). The TSBCK can be slaved to three different clock sources: Transmit Clock Input (TCKI), Transmit System Bus Clock Input ...

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Circuit Description 2.3 System Bus 64-Bit Elastic In 64-bit Elastic mode, the slip buffer total depth is 64 bits and the initial throughput delay is 32 bits, or one-half of the total depth. Similar to Normal mode, Elastic mode ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Figure 2-19. Transmit Framing and Timebase Alignment Options TPCMI TFSYNCI TMSYNCI TSB Offset TFSYNCO FSYNC MSYNC TMSYNCO TSB Timebase A TSB Aligns to TPCMI (EMBED = 0) B TSB Aligns to TX (TSB_ALIGN = 1) NOTE(S): (1) ...

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Circuit Description 2.3 System Bus Note that the online framer's multiframe search status is not directly reported to the processor, but instead is monitored by examination of transmit error status: TMERR, TSERR, and TCERR [addr 00B]. If the system ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers The status of the offline framer can be monitored using the Offline Framer Status register [FSTAT; addr 017]. The register reports the following: whether the offline framer is looking at the receive or transmit data streams (RX/TXN); ...

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... Transmitter 2.4 Transmitter The Transmitter (XMTR) inserts T1/E1 overhead data and outputs single rail NRZ data from the TSB or ZCS-encoded P and N rail NRZ data. The CX28395 only provides single rail NRZ transmit signals. The XMTR, Data Links, Test Pattern Generator, In-Band Loopback Code Generator, Overhead ...

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... DL1 and DL2 each contain a 64-byte transmit buffer which function either as programmable length circular buffers in transparent (unformatted) mode full-length data FIFOs in formatted (HDLC) mode. 100054E DL3 signals are not provided on the CX28395. Therefore, DL3_TS must be written disable the DL3 transmitter and prevent transmit data corruption. TS9 ...

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Circuit Description 2.4 Transmitter DL1 and DL2 are configured identically, except for their offset in the register map. The DL1 address range is 0A4 to 0AE, and the DL2 address range is 0AF to 0B9. From this point on, ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 2.4.2.3 Time Slot and Time slot and bit selection is done through the DL1 Time Slot Enable [DL1_TS; Bit Selection addr 0A4] and DL1 Bit Enable [DL1_BIT; addr 0A5] registers. DL1_TS selects which frames and which time ...

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Circuit Description 2.4 Transmitter 2.4.2.6 Programming The Transmit Data Link Controller can be programmed according to the system the Data Link Controller CPU bandwidth. For systems with sufficient CPU bandwidth, the data link status can be polled, and the ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Figure 2-23. Interrupt-Driven Transmit Data Link Processing Message 0x00 Block 1 0x20 Block 2 0x40 Block 3 0x60 Block 4 100054E Main Line Code Transmit Message Write Block/Byte to FIFO Return Interrupt Service Routine Interrupt Occurred Read ...

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Circuit Description 2.4 Transmitter 2.4.2.7 PRM Generator In T1 applications, Performance Report Messages (PRMs) are HDLC messages containing path identification and performance monitoring information. If automatic performance report insertion is selected [AUTO_PRM; addr 0AA], a performance report is generated ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 2.4.4 Overhead Pattern Generation The transmit overhead generation circuitry provides the ability to insert all of the overhead associated with the Primary Rate Channel. The following types of overhead pattern generation are supported: Framing patterns, Alarm patterns, ...

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Circuit Description 2.4 Transmitter Yellow Alarm Generation Yellow Alarm, also referred to as RAI (Remote Alarm Indication bit pattern inserted into the transmit stream to alert far-end equipment that the local receiver cannot recover data. Yellow Alarm/RAI ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Multiframe Yellow Alarm In E1 CAS framing modes, Multiframe Yellow Alarm is inserted into the transmit Generation stream to alert far-end equipment that local received multiframe alignment is not recovered. E1 Multiframe Yellow Alarm is transmitted by ...

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Circuit Description 2.4 Transmitter 2.4.5 Test Pattern Generation The transmit test pattern generation circuitry overwrites the transmit data with various test patterns and permits logical and frame-bit error insertion. This feature is particularly useful for system diagnostics, production testing, ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Change Of Frame Alignments (COFAs) are controlled by the TCOFA and BSLIP bits in the TERROR register. TCOFA commands a 1-bit shift in the location of the transmit frame alignment by deleting (or inserting) a 1-bit position ...

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Circuit Description 2.4 Transmitter The HDB3 line code replaces four consecutive zeros by 000V or B00V code, where AMI pulse and bipolar violation (see encoder selects the code that will force the BPV ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers The output on TPOSO/TNEGO can be changed from dual rail bipolar to NRZ unipolar data (TNRZO) and to multiframe sync clock (MSYNCO), using the Transmit NRZ Data (TNRZ) bit in TCR1[addr 071]. illustrate transmit signal timing for ...

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Circuit Description 2.4 Transmitter Figure 2-26. NRZ Mode Transmit Signals MSYNCO TCKO Bit 8 TNRZO Time Slot 24, Frame 12 (SF) or Frame 24 (ESF) MSYNCO TCKO TNRZO Bit 6 Time Slot 31, Frame 15 2-54 F-bit Bit 1 ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 2.5 Microprocessor Interface The Microprocessor Interface (MPU) provides the capability to configure the device, read status registers and counters, and respond to interrupts (see Figure processors. In the Intel mode, the address and data are multiplexed; in ...

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Circuit Description 2.5 Microprocessor Interface 2.5.1 Address/Data Bus In Non-Multiplexed Address Mode, A[11:0] (A[10:0] for CX28394) provides the address for the register access. In Multiplexed Address Mode, A[11:8] (A[10:8] for CX28394) and AD[7:0] provide the address. In both modes, ...

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... MIR Register NOTE(S): (1) In CX28395, INTR1* is provided for Framers 1-8, and INTR2* is provided for Framers 9-16. 100054E Read MIR and SER_STAT registers to determine which framer or framers caused the interrupt or whether LIU serial operation occurred. For each interrupting framer, read IRR to determine which ISR contains the interrupt event or events ...

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Circuit Description 2.5 Microprocessor Interface 2.5.4 Device Reset The device contains four reset methods All four methods result in device outputs placed in a high-impedance state and configuration registers set to default values as shown ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 2.6 Loopbacks The device provides a complete set of loopbacks for diagnostics, maintenance, and troubleshooting for each framer. All loopbacks perform clock and data switching, if necessary. 2.6.1 Remote Line Loopback The line loopback loops the RCVR ...

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Circuit Description 2.6 Loopbacks 2.6.4 Local Framer Loopback The local framer loopback loops the transmit line encoder outputs to the receive line decoder inputs. Transmitter output is not affected by the activation of this loopback. The local framer loopback ...

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... CX28398: SERCS1* and SERCS2*. The CX28394 provides a single SERCS* chip select line. On the CX28395, the serial interface is not accessable. The serial interface uses a 16-bit process for each write or read operation. During a write operation, a 16-bit word and [SER_DAT ...

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... A Boundary Scan Description Language TCK TMS JTAG Port TRST* TDI Table 2-8 lists the JTAG instructions along with their codes. Instruction Code BYPASS 111 SAMPLE/PRELOAD 001 EXTEST 000 IDCODE 010 Private xxx Conexant CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers TDO1 (CX28395) TDO2 100054_003 100054E ...

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... NOTE(S): (1) Consult factory for current version number. Table 2-10. CX28395 Device Identification JTAG Register (1) Version Part Number ...

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Circuit Description 2.8 Joint Test Access Group 2-64 CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Conexant 100054E ...

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Registers 3.1 Address Map Registers shown with a default setting are reset to the indicated value following power up, software RESET (CRO; addr 001), GRESET (FCR; addr 080), or hardware reset (RST* pin). Addresses 000 (hex) to 1FF ...

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... Registers 3.1 Address Map Table 3-3. Address Offset Map (CX28395) Framer NOTE(S): 1. Global registers at 000 and 080–083 for framers 1–8 may be accessed at any of the first 8 offsets. 2. Global registers at 000 and 080–083 for framers 9–16 may be accessed at any of the second 8 offsets. ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 3-4. Address Map ( Address Block Acronym (Hex) 000 DID 080 FCR 081 MIR 082 MIE 083 TEST 001 CR0 003 IRR 004 ISR7 005 ISR6 006 ISR5 007 ISR4 008 ISR3 009 ISR2 ...

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Registers 3.1 Address Map Table 3-4. Address Map ( Address Block Acronym (Hex) 022 SER_CTL 023 SER_DAT 024 SER_STAT 025 SER_CONFIG 026 RAM TEST 040 RCR0 041 RPATT 042 RLB 043 LBA 044 LBD 045 RALM 046 ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 3-4. Address Map ( Address Block Acronym (Hex) 070 TCR0 071 TCR1 072 TFRM 073 TERROR 074 TMAN 075 TALM 076 TPATT 077 TLB 078 LBP 07B TSA4 07C TSA5 07D TSA6 07E TSA7 ...

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Registers 3.1 Address Map Table 3-4. Address Map ( Address Block Acronym (Hex) 0AF DL2_TS 0B0 DL2_BIT 0B1 DL2_CTL 0B2 RDL2_FFC 0B3 RDL2 0B4 RDL2_STAT 0B6 TDL2_FEC 0B7 TDL2_EOM 0B8 TDL2 0B9 TDL2_STAT 0BA DL_TEST1 0BB DL_TEST2 ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 3-4. Address Map ( Address Block Acronym (Hex) 100–11F TPCn 120–13F TSIGn 140–15F TSLIP_LOn 160–17F TSLIP_HIn ...

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... DID[7] DID[6] DID[5] Device Revision—A value of 0x4 indicates the current revision. DID[7:4] Device ID—A value of 0x8 indicates the CX28398 or CX28395. A value of 0x4 indicates the DID[3:0] CX28394. 080—Framer Control Register (FCR) Unused bits are reserved and should be written ...

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... SBIMODE[0]: 081—Master Interrupt Request (MIR) CX28394 — — — CX28398 and CX28395 MIR[7] MIR[6] MIR[5] An active MIR bit indicates which framer has active interrupts. An MIR bit is latched active MIR[7:0] (high) whenever any bit in the Interrupt Request Register (IRR[7:0]; addr 003–0B) is set to report an interrupt event ...

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... Global Control and Status Registers 082—Master Interrupt Enable (MIE) CX28394 — — — CX28398 and CX28395 MIE[7] MIE[6] MIE[5] MIE is a global interrupt enable for each framer. Writing a one to an MIE bit enables the MIE[7:0] corresponding framer’s IRR bit to be latched in MIR (addr 081) and to activate the INTR* output ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 3.3 Primary Control and Status Register 001—Primary Control Register (CR0) Unused bits are reserved and should be written RESET — RINCF Framer Reset—When written the microprocessor, RESET initiates an ...

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Registers 3.3 Primary Control and Status Register Receiver Framer Mode—Establishes the offline framer's search criteria for recovery of frame RFRAME[3:0] alignment (reframe). Also works in conjunction with the RLOFA–RLOFD bits [addr 040] to establish the online framer's criteria for ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 3.4 Interrupt Control Register 003—Interrupt Request Register (IRR) An IRR bit is latched active (high) whenever an enabled interrupt source reports an interrupt event in the corresponding Interrupt Status Register [ISR7–ISR0; addr 004–00B]. IRR is latched until ...

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Registers 3.4 Interrupt Control Register Data Link Controller 2 or BOP Receive—Indicates that a transmit or receive interrupt issued DL2 by DL2 or BOP transceiver has received a valid priority codeword and updated RBOP [addr 0A2]. Processor reads ISR1 ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 3.5 Interrupt Status Registers An Interrupt Status Register (ISR) bit is latched active (high) whenever its corresponding interrupt source reports an interrupt event. The processor reads ISR to clear all latched ISR bits. If the corresponding interrupt ...

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Registers 3.5 Interrupt Status Registers 004—Alarm 1 Interrupt Status (ISR7) All events reported in ISR7 are from dual-edge sources, except Receive Pulse Density Violation [RPDV]. Any transition of real-time status in Alarm 1 Status Register [ALM1; addr 047] forces ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 005—Alarm 2 Interrupt Status (ISR6) All events reported in ISR6 are from dual-edge sources, except the one-second timer [ONESEC] and Transmit Pulse Density Violation [TPDV]. Any transition of real-time status in the Alarm 2 Status Register [ALM2; ...

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Registers 3.5 Interrupt Status Registers 006—Error Interrupt Status (ISR5) All events in ISR5 are from rising edge sources. Each event is latched active high and held according to the LATCH_ERR bit [addr 046] and triggers an interrupt if the ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 007—Counter Overflow Interrupt Status (ISR4) All count overflow events in ISR4 are from rising edge sources. Each event is latched active high when the respective error counter [addr 050–05A] reaches its maximum count value, but only while ...

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Registers 3.5 Interrupt Status Registers Receive Signaling Stack—Indicates that one or more signaling bit changes were detected RSIG during the prior receive multiframe, and that new ABCD (robbed bit or CAS) signaling is available on the Receive Signaling Stack ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 00A—Data Link 2 Interrupt Status (ISR1) All events in ISR1 are from rising edge sources. Each event is latched active high and held until the processor read clears ISR1. Each event triggers an interrupt if the corresponding ...

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Registers 3.5 Interrupt Status Registers 00B—Pattern Interrupt Status (ISR0) All events in ISR0 are from rising edge sources. Each event is latched active high and held until the processor read clears ISR0. Each event triggers an interrupt if the ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 3.6 Interrupt Enable Registers Writing a one to an IER bit allows that specific interrupt source to activate its respective ISR bit, the associated MIR bit. While cleared, each IER bit allows that source to activate its ...

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Registers 3.6 Interrupt Enable Registers 00E—Error Interrupt Enable Register (IER5) Unused bits are reserved and should be written TSLIP RSLIP — Enable TSLIP Interrupt TSLIP Enable RSLIP Interrupt RSLIP Enable CERR Interrupt CERR Enable ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 010—Timer Interrupt Enable Register (IER3 TSIG TMSYNC TMF Enable TSIG Interrupt TSIG Enable TMSYNC Interrupt TMSYNC Enable TMF Interrupt TMF Enable TFRAME Interrupt TFRAME Enable RSIG Interrupt RSIG Enable RMSYNC Interrupt RMSYNC Enable RMF ...

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Registers 3.6 Interrupt Enable Registers 012—Data Link 2 Interrupt Enable Register (IER1 RBOP RFULL2 RNEAR2 Enable RBOP Interrupt RBOP Enable RFULL Interrupt RFULL2 Enable RNEAR Interrupt RNEAR2 Enable RMSG Interrupt RMSG2 Enable TDLERR Interrupt TDLERR2 Enable ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 3.7 Primary Control and Status Registers 014—Loopback Configuration Register (LOOP) Unused bits are reserved and should be written — — — Enable Remote Payload Loopback—Payload from receiver replaces payload on transmitter PLOOP ...

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... TDLI pins and which receive and transmit time slots are accompanied by a gated RDLCKO and TDLCKO output. Refer to Figure 2-21, Transmit External Data Link the entire receive data bit stream, and only selective time slots are marked by RDLCKO. DL3 is not accessible on the CX28395 device, therefore, DL3_TS must be written to 00. CX28394, CX28398 7 6 ...

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... The selected transmit data link bits are sampled from the TDLI pin on the falling edge of TDLCKO to replace normal transmitted data. DL3_BIT has no effect when DL3_TS selects T1 Fbits or when the DL3EN bit is inactive. DL3 is not accessible on the CX28395 device disable DL3 bit 1 = enable DL3 bit 017— ...

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Registers 3.7 Primary Control and Status Registers Framer Search Timeout—Cleared when the offline framer transitions to its ACTIVE state. If TIMEOUT multiple frame candidates exist over the entire mode-dependent timeout interval (refer to Table 3-8), TIMEOUT is latched active ...

Page 153

... Enable Transmit Data Link—Select which signals are present on bimodal TDLCKO and TDL_IO TDLI. When active Transmit Data Link Clock Out (TDLCKO) and Transmit Data Link Data Out (TDLO) are enabled. On the CX28395 device, TDL3 is not available and TDL_IO must be written select TINDO and TSIGI 1 = select Transmit Data Link Bidirectional RFSYNC Input/Output Mode— ...

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Registers 3.7 Primary Control and Status Registers Bidirectional TFSYNC Input/Output Mode—TFSYNC_IO programming is dependent on TFSYNC_IO transmit framer and system bus modes as shown TFSYNC input 1 = TFSYNC output Bidirectional TMSYNC Input/Output mode—TMSYNC_IO programming is ...

Page 155

... TDL_OE TDLCKO Output Buffer Control—When enabled, TDLCKO is output according to DL3_TS TDL_OE and DL3_BIT [addr 015, 016]. TDL_OE should be written the CX28395 device TDLCKO output enabled 1 = TDLCKO output three-stated RDLCKO and RDLO Output Buffer Control—When enabled, both bimodal signals are output RDL_OE by their respective internal circuits ...

Page 156

Registers 3.7 Primary Control and Status Registers 01A—Clock Input Mux (CMUX) Unused bits are reserved and should be written — RSBCK — RSBCK Source Select—Internal clock mux selects from one of two clock signals ...

Page 157

CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 021—Receive Line Code Status (RSTAT — — ZCSUB Zero Code Substitution—Indicates one or more B8ZS/HDB3 substitution patterns have been ZCSUB detected on receiver input data, depending on T1/E1N line rate selection. ZCSUB is reported ...

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... Registers 3.8 Serial Interface Registers 3.8 Serial Interface Registers These registers are not used on the CX28395 device. 022—Serial Control (SER_CTL) Writing to SER_CTL initiates a serial interface read or write operation. During a write operation, a 16-bit word, consisting of SER_CTL and SER_DAT, is transmitted to the LIU. During a read operation, SER_CTL is transmitted and 8-bit data from the LIU is received and placed in SER_DAT register ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 025—Serial Configuration (SER_CONFIG) Unused bits are reserved and should be written SER_CS SER_CLK — Serial Interface Chip Select 1 SER_CS 0 = sets external SERCS1* signal low 1 = sets external SERCS2* ...

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Registers 3.9 Receiver Registers 3.9 Receiver Registers 040—Receiver Configuration (RCR0 RAMI RABORT RFORCE Receive AMI Encoded Inputs—Disables B8ZS/HDB3 decoding for AMI formatted receive RAMI signals. Otherwise, ZCS decoder replaces 000VB0VB code (B8ZS) with 8 zeros in ...

Page 161

CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Receive B8ZS/HDB3 Zero Code Substitution (affects only BPV/LCV/EXZ counting)—When RZCS set, the ZCS decoder does not include bipolar violations received as part of a B8ZS/HDB3 code in the LCV error count [addr 054, 055]. Otherwise, all bipolar ...

Page 162

Registers 3.9 Receiver Registers Table 3-12. Receive PRBS Test Pattern Measurements ( FRAMED ZLIMIT PRBS Zero Limit—Determines the number of consecutive zeros allowed within the ...

Page 163

CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Loopback Activate Code Length—Selects the number of loopback pattern bits from LBA UP_LEN[1:0] [addr 043] that are compared to received data. This is done in order to determine whether a Loopback Activate Code [LOOPUP; addr 048] has ...

Page 164

Registers 3.9 Receiver Registers 045—Receive Alarm Signal Configuration (RALM) Unused bits are reserved and should be written — DIS_LCV FS_NFAS Disable LCV indication and counting. Primarily used in configurations where receive data is DIS_LCV ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 3-13. Receive Yellow Alarm Set/Clear Criteria ( Mode YJ Set for 1 multiframe (1.5 ms) if frame 12 contains Fs bit = 1. Cleared for 1 multiframe if frame 12 contains Fs bit = ...

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Registers 3.9 Receiver Registers 046—Alarm/Error/Counter Latch Configuration (LATCH) Unused bits are reserved and should be written — — — Stop Error Count during RLOF/RLOS/RAIS—If enabled, error count registers [addr 050–057] STOP_CNT are suspended at ...

Page 167

CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 047—Alarm 1 Status (ALM1) ALM1 reports current status of receive alarms. Any change in the current status activates the corresponding interrupt status bit [ISR7; addr 004 RMYEL RYEL — Receive Multiframe Yellow Alarm—Real-time or ...

Page 168

Registers 3.9 Receiver Registers Receive Alarm Indication Signal—Criteria for detection and clearance of RAIS per ITU G.775 RAIS and ANSI T1.231. Mode Receive Loss of Signal or Receive Clock—Reports loss of receive clock (RCKI) or ...

Page 169

CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Receive Loss of Frame Alignment—Real-time or integrated RLOF status depends on selected RLOF receive framer mode, out of frame criteria [RLOFA–RLOFD; addr 040], and integration mode [RLOF_INTEG; addr 045]. Refer to frame bits are monitored. Refer to ...

Page 170

Registers 3.9 Receiver Registers 049—Alarm 3 Status (ALM3) Reports real-time status of the receive framer (not affected by ONESEC latch mode), and miscellaneous latched error status (SEF and RMAIS). Any change of the logical OR of (FRED or MRED ...

Page 171

CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 3.10 Performance Monitoring Registers If the counter overflow interrupt [IER4; addr 00F] is enabled for the respective Performance Monitoring counter, the counter is allowed to roll over after reaching its maximum count value. If the overflow interrupt ...

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Registers 3.10 Performance Monitoring Registers 054—Line Code Violation Counter LSB (LCV LCV[7] LCV[6] LCV[5] BPV and EXZ (if EXZ_LCV enabled) Error Count LCV[7:0] 055—Line Code Violation Counter MSB (LCV) If LATCH_CNT [addr 046] is inactive, reading ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 059—PRBS Bit Error Counter MSB (BERR BERR Count (suspended if BSTART = 0) BERR[11:8] 05A—SEF/FRED/COFA Alarm Counter (AERR) Reading AERR clears the SEF[1:0], COFA[1:0] and FRED[3:0] count values ...

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Registers 3.11 Receive Sa-Byte Buffers 3.11 Receive Sa-Byte Buffers Five receive Sa-Byte buffers [RSA4–RSA8] are double-buffered. All five registers are updated with the Sa-bits received in TS0 of odd frames at each receive multiframe interrupt [RMF; addr 008]. Bit ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 05D—Receive Sa6 Byte Buffer (RSA6 RSA6[7] RSA6[6] RSA6[5] Sa6 bit received in frame 15 RSA6[7] Sa6 bit received in frame 13 RSA6[6] Sa6 bit received in frame 11 RSA6[5] Sa6 bit received in frame ...

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Registers 3.11 Receive Sa-Byte Buffers 05F—Receive Sa8 Byte Buffer (RSA8 RSA8[7] RSA8[6] RSA8[5] Sa8 bit received in frame 15 RSA8[7] Sa8 bit received in frame 13 RSA8[6] Sa8 bit received in frame 11 RSA8[5] Sa8 bit ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 3.12 Transmitter Registers 070—Transmit Framer Configuration (TCR0) TCR0 selects the offline framer's criteria for recovery of transmit frame alignment and determines the output of transmit frame and alarm formatters overhead bits. In addition, TCR0 works in conjunction ...

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Registers 3.12 Transmitter Registers Frame formatter generates Ft, Fs, FPS, FAS, MFAS, and CRC bits. Alarm formatter generates TFRAME[3:0] YB2, YJ, Y0, and Y16 bits. Frame and alarm overhead formats are selected by TFRAME[3:0] and T1/E1N settings as given ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Table 3-16. T1 Transmit Framer Modes (T1/E1N = 1) TFRAME Framer Mode 0000 FT Only 0100 SF 0101 SF + JYEL 100X SLC 0001 ESF + No CRC 1100 ESF + Mimic CRC 1101 ESF + Force ...

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Registers 3.12 Transmitter Registers Table 3-18. Criteria for T1 Loss/Recovery of Transmit Frame Alignment Mode FT Only Terminal Frame Alignment is recovered when: One and only one valid Ft pattern (1010) is found in 12 alternate F-bit locations (3 ...

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... TNRZ non-return to zero unipolar data (TNRZO) and transmit multiframe sync (MSYNCO). Both outputs are clocked on the rising edge of transmitter clock (TCKI). TNRZ must be written the CX28395 device TPOSO/TNEGO encoded per TZCS[1: TPOSO/TNEGO replaced by TNRZO/MSYNCO MSYNCO active (high) always marks the first bit of transmit multiframe according to NOTE: the selected transmit framer mode ...

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Registers 3.12 Transmitter Registers Transmit Loss Of Frame Criteria—Determines the number of frame errors that the online TLOFC–TLOFA framer must detect before declaring loss of frame alignment [TLOF; addr 048]. Refer to TFRAME [addr 070] to find which frame ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 072—Transmit Frame Format (TFRM) TFRM controls the insertion of overhead bits generated by transmit frame and alarm formatters. Bypassed overhead bits flow transparently from TPCMI system bus input through TSLIP buffer. Unused bits are reserved and should ...

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Registers 3.12 Transmitter Registers 073—Transmit Error Insert (TERROR) Transmit error insertion capabilities are provided for system diagnostic, production test, and test equipment applications. Writing a one to any TERROR bit injects a single occurrence of the respective error on ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Inject Line Code Violation—Injects a single LCV error, depending on line mode and ZCS TVERR selected mode, the LCV injector waits for transmission of two consecutive pulses on the data output before performing BPV error ...

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Registers 3.12 Transmitter Registers 075—Transmit Alarm Signal Configuration (TALM) Unused bits are reserved and should be written — AISCLK AUTO_MYEL Enable Automatic ACKI Switching—When AISCLK is active and the clock monitor reports a AISCLK ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Manual/Automatic Transmit Alarm Indication Signal—When activated manually (TAIS) or AUTO_AIS /TAIS automatically (AUTO_AIS), the alarm formatter replaces all data output on TPOSO/TNEGO/TNRZO with an unframed all ones signal (AIS). This includes replacing data from the receiver during ...

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Registers 3.12 Transmitter Registers Table 3-21. Transmit PRBS Test Pattern Measurements FRAMED ZLIMIT ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 078—Transmit Inband Loopback Code Pattern (LBP) Unused bits are reserved and should be written LBP[1] LBP[2] LBP[3] First bit transmitted LBP[1] Second bit transmitted LBP[2] Third bit transmitted LBP[3] Fourth bit transmitted ...

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Registers 3.13 Transmit Sa-Byte Buffers 3.13 Transmit Sa-Byte Buffers Five transmit Sa-Byte buffers (TSA4–TSA8) are used to insert Sa-bits in TS0. The entire group of 40 bits is sampled every 16 frames, coincident with the TMF interrupt boundary [addr ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 07D—Transmit Sa6 Byte Buffer (TSA6 TSA6[7] TSA6[6] TSA6[5] Sa6 bit transmitted in frame 15 TSA6[7] Sa6 bit transmitted in frame 13 TSA6[6] Sa6 bit transmitted in frame 11 TSA6[5] Sa6 bit transmitted in frame ...

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Registers 3.13 Transmit Sa-Byte Buffers 07F—Transmit Sa8 Byte Buffer (TSA8 TSA8[7] TSA8[6] TSA8[5] Sa8 bit transmitted in frame 15 TSA8[7] Sa8 bit transmitted in frame 13 TSA8[6] Sa8 bit transmitted in frame 11 TSA8[5] Sa8 bit ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 3.14 Bit-Oriented Protocol Registers The Bit Oriented Protocol (BOP) transceiver sends and receives BOP messages, including ESF Yellow Alarm. These messages consist of repeated 16-bit patterns with an embedded 6-bit codeword. The BOP message channel is configured ...

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Registers 3.14 Bit-Oriented Protocol Registers RBOP Message Length—Selects the number of successive identical 16-bit patterns that are RBOP_LEN[1:0] needed to qualify receipt of a single BOP message and to update RBOP [addr 0A2] with the received codeword. At this ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 0A1—Transmit BOP Codeword (TBOP — — TBOP[5] 6th bit transmitted TBOP[5] 5th bit transmitted TBOP[4] 4th bit transmitted TBOP[3] 3rd bit transmitted TBOP[2] 2nd bit transmitted TBOP[1] Transmit BOP codeword, 1st bit transmitted TBOP[0] ...

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Registers 3.14 Bit-Oriented Protocol Registers 0A3—BOP Status (BOP_STAT) Real-time status of the BOP transmitter and receiver is reported primarily for diagnostic purposes TBOP_ACTIVE RBOP_ACTIVE — TBOP Active—Remains set for the entire length of a message as ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers 3.15 Data Link Registers Each framer contains two independent Data Link Controllers (DL1, DL2), which are programmed to send and receive HDLC formatted or unformatted serial data over any combination of bits within a selected time slot. ...

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Registers 3.15 Data Link Registers 0A5—DL1 Bit Enable (DL1_BIT DL1_BIT[7] DL1_BIT[6] DL1_BIT[5] DL1 Bit Select—Works in conjunction with DL1_TS [addr 0A4] to select one or more time DL1_BIT[7:0] slot bits for data link input and output. ...

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CX28394/28395/28398 Quad/x16/Octal—T1/E1/J1 Framers Non-FCS mode passes all message bits that exist between the opening and closing FLAG characters through the FIFOs, without generating or checking FCS bits. Non-FCS mode allows the processor to generate and check the entire contents of ...

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Registers 3.15 Data Link Registers For example, SLC applications monitor Fs bits during even frames for a total of 36 bits monitored out of 72 frames. Using Pack6 mode, that group bits from each SLC multiframe ...

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