RS8953BEPF Conexant Systems, Inc., RS8953BEPF Datasheet

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RS8953BEPF

Manufacturer Part Number
RS8953BEPF
Description
HDSL channel unit
Manufacturer
Conexant Systems, Inc.
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
RS8953BEPF
Manufacturer:
CONEXANT
Quantity:
40
Channel
RS8953B/8953SPB
HDSL Channel Unit
The RS8953B is a High-Bit-Rate Digital Subscriber Line (HDSL) channel unit designed
to perform data, clock, and format conversions necessary to construct a Pulse Code
Multiplexed (PCM) channel from one, two, or three HDSL channels. The PCM channel
consists of transmit and receive data, clock and frame sync signals configured for
standard T1 (1544 kbps), standard E1 (2048 kbps), or custom (Nx64 kbps) formats.
The PCM channel connects directly to a Bt8370 T1/E1 Controller or similar T1/E1 device.
Connection to other network/subscriber physical layer devices is supported by the
custom PCM frame format. Three identical HDSL channel interfaces consist of serial
data and clock connected to a Bt8970 HDSL Transceiver or similar 2B1Q bit pump
device. The RS8953SPB contains one HDSL channel interface.
interface. One common register group configures the PCM interface formatter,
Pseudo-Random Bit Sequence (PRBS) generator, Bit Error Rate (BER) meter, timeslot
router, Digital Phase Lock Loop (DPLL) clock recovery, and PCM Loopbacks (LB). Three
groups of HDSL channel registers configure the elastic store FIFOs, overhead MUXes,
receive framers, payload mappers, and HDSL loopbacks. Status registers monitor
received overhead, DPLL, FIFO, and framer operations, including CRC and FEBE error
counts.
latest ETSI RTR/TM-03036 standards. C-language software for all standard T1/E1
configuration and startup procedures is implemented on Conexant's HDSL Evaluation
Module (Bt8973EVM) and is available under a no-fee license agreement. RS8953B
software can also be developed for non-standard HDSL applications or to interoperate
with existing HDSL equipment.
Functional Block Diagram
Data Sheet
Insert
Drop
PCM
Control and status registers are accessed via the Microprocessor Unit (MPU)
The RS8953B adheres to Bellcore TA-NWT-001210 and FA-NWT-001211 and the
Microprocessor
LB
Registers
MPU
PRBS
BER
PLL Filter
Elastic
Elastic
DPLL
Store
Store
HOH Mux
Payload
Mapper
Mapper
Stuff
Receive
Framer
Decoder
Encoder
2B1Q
2B1Q
LB
Channels
HDSL
1, 2, 3
Distinguishing Features
• Supports All HDSL Bit Rates
• T1/E1 Primary Rate (PCM) Channel
• HDSL Channels
• Programmable Data Routing
• Intel
• CMOS technology, 3.3 V operation
• 68-pin PLCC or 80-pin PQFP
Applications
• Full, Fractional or Multipoint T1/E1
• Single and Multichannel Repeaters
• Voice Pair Gain Systems
• Wireless LAN/PBX
• PCS, Cellular Base Station
• Fiber Access/Distribution
• Loop Carrier, Remote Switches
• Subscriber Line Modem
– 2 pair T1 standard (784 kbps)
– 2 pair E1 standard (1168 kbps)
– 3 pair E1 standard (784 kbps)
– 1/2/3 pair custom (Nx64 kbps,
– Connects to Conexant E1/T1
– Framed or unframed mode
– Sync/Async payload mapping
– Clock recovery/jitter attenuation
– PRBS/fixed test patterns
– BER measurement
– Connects to Conexant ZipWire
– Three independent serial channels
– Central, remote, or repeater
– Overhead (HOH) management
– Programmable path delays
– Error performance monitoring
– Software controlled EOC and IND
– Auxiliary payload/Z-bit data link
– Master loop ID and interchange
– Auto tip/ring reversal
– PCM timeslots – HDSL payload
– Drop/Insert – HDSL payload
– Auxiliary – HDSL payload
– PRBS/Fixed – PCM or HDSL
– PCM and HDSL loopbacks
N=2-36)
Framers
Transceivers
®
or Motorola
®
March 30, 1999
MPU interface
D8953BDSB

Related parts for RS8953BEPF

RS8953BEPF Summary of contents

Page 1

RS8953B/8953SPB HDSL Channel Unit The RS8953B is a High-Bit-Rate Digital Subscriber Line (HDSL) channel unit designed to perform data, clock, and format conversions necessary to construct a Pulse Code Multiplexed (PCM) channel from one, two, or three HDSL channels. The ...

Page 2

... Ordering Information Order Number RS8953BEPF 80–Pin Plastic Quad Flat Pack (PQFP) RS8953BEPJ 68–Pin Plastic Leaded Chip Carrier (PLCC) RS8953SPB EPF 80–Pin Plastic Quad Flat Pack (PQFP) RS8953SPB EPJ 68–Pin Plastic Leaded Chip Carrier (PLCC) Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use ...

Page 3

Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 3.2.2.1 Receive Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

RS8953B/8953SPB HDSL Channel Unit 0x00—Transmit Embedded Operations Channel (TEOC_LO 5-10 0x01—Transmit Embedded Operations Channel (TEOC_HI ...

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Table of Contents 0xC2—TSER Multiframe Bit Location (TMF_LOC 5-26 0xC3—RSER Frame ...

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RS8953B/8953SPB HDSL Channel Unit 0xE7—Command Register 3 (CMD_3 ...

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Table of Contents 0x42—PRA Transmit Monitor Register 1 (TX _PRA_MON1 5-67 0x43—PRA Transmit E-Bits Counter (TX _PRA_E_CNT ...

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RS8953B/8953SPB HDSL Channel Unit 7.1.1 Bit Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 10

Table of Contents x Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...

Page 11

RS8953B/8953SPB HDSL Channel Unit List of Figures Figure 1-1. HTU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 12

List of Figures Figure 3-27. An Overview of the PRA Transfer of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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RS8953B/8953SPB HDSL Channel Unit List of Tables Table 2-1. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Tables xiv Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...

Page 15

HDSL Systems 1.1 HTU Applications The High-Bit-Rate Digital Subscriber Line (HDSL simultaneous full-duplex transmission scheme which uses twisted-pair wire cables as the physical medium to transport signals between standard types of network or subscriber communication interfaces. A ...

Page 16

HDSL Systems 1.1 HTU Applications Figure 1-1 T1/E1 signals. T1/E1 transceivers convert T1/E1 interface signals into a Pulse Code Multiplexed (PCM) channel of clock, serial data, and optional frame sync. ZipWire transceivers convert 2B1Q line signals to HDSL channels ...

Page 17

RS8953B/RS8953SPB HDSL Channel Unit 1.1.2 Fractional Transport Figure 1-3 channel bandwidth is transported over one or more HDSL wire pairs. The RS8953B provides drop/insert indicator signals to control external data MUXes and internal routing tables to map timeslots from either ...

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HDSL Systems 1.1 HTU Applications 1.1.3 Switching Systems Figure 1-4 multiplexer system that uses multiple HDSL lines to transport Nx64 or standard T1/E1 applications. The RS8953B’s PCM timeslot router contains 64 table entries that extends the maximum PCM channel ...

Page 19

RS8953B/RS8953SPB HDSL Channel Unit 1.1.4 Loop Carrier/Pair Gain Figure 1-5 bank of voice and/or data subscriber line interfaces using an Nx64 bus. The total number of subscriber lines determines the PCM channel rate and determines how many HDSL wire pairs ...

Page 20

HDSL Systems 1.1 HTU Applications 1.1.5 Point-to-Multipoint Figure 1-6 remote sites in a Point-to-Multipoint (P2MP) application. The number of HDSL wire pairs and PCM channel rates at each site is variable. The RS8953B provides the ability to measure and ...

Page 21

RS8953B/RS8953SPB HDSL Channel Unit 1.1.6 Subscriber Modem Figure 1-7 delivers PCM data directly to the RS8953B. Alternately, a multichannel communications controller such as the Bt8071A can be used to manage the transfer of data between the CPU and PCM channel ...

Page 22

HDSL Systems 1.2 System Interfaces 1.2 System Interfaces System interfaces and associated signals for the RS8953B functional circuit blocks are shown in and signals are defined in The single-pair version (RS8953SPBEPF and RS8953SPBEPJ) only supports HDSL Channel 1. HDSL ...

Page 23

Pin Descriptions 2.1 Pin Assignments The RS8953B pin assignments for the 68–pin Plastic Leaded Chip Carrier (PLCC) package are shown in assignments for the 80–pin Plastic Quad Flat Pack (PQFP) are shown in Figure 2-3 Table 2-1 coded as ...

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Pin Descriptions 2.1 Pin Assignments Figure 2-1. Three-Pair PLCC Pin Assignments RDAT1 10 AD[0] 11 AD[1] 12 AD[2] 13 AD[3] 14 AD[4] 15 AD[5] 16 AD[6] 17 AD[7] 18 VCC 19 EXCLK 20 INSDAT 21 INSERT/RAUX2 22 INTR* 23 ...

Page 25

RS8953B/8953SPB HDSL Channel Unit Figure 2-2. Single-Pair PLCC Pin Assignments RDAT1 10 AD[0] 11 AD[1] 12 AD[2] 13 AD[3] 14 AD[4] 15 AD[5] 16 AD[6] 17 AD[7] 18 VCC 19 EXCLK 20 INSDAT 21 (1) INSERT 22 INTR* 23 TMSYNC ...

Page 26

... ROH2 69 QCLK2 70 GND 71 GND 72 BCLK2 TDAT2 75 RDAT2 76 GND 77 BCLK1 78 ROH1 79 TDAT1 2-4 RS8953BEPF Conexant RS8953B/8953SPB HDSL Channel Unit 40 MCLK CS DROP/RAUX1 36 GND 35 TMS TD0 32 TDI 31 TCK 30 RST* RD* 29 RSER ...

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RS8953B/8953SPB HDSL Channel Unit Figure 2-4. Single-Pair PQFP Pin Assignments GND 67 ...

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Pin Descriptions 2.1 Pin Assignments Table 2-1. Pin Assignments ( 80-Pin 68-Pin Signal PQFP PLCC 3 10 RDAT1 5 11 AD[ AD[ AD[ AD[ AD[ AD[5] 11 ...

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RS8953B/8953SPB HDSL Channel Unit 2.2 Signal Definitions Table 2-2. Signal Definitions ( Signal Name I/O MPUSEL MPU Select I AD[0:7] Address/Data Bus I/O CS* Chip Select I ALE Address Latch I Enable RD* Read Strobe I WR* Write ...

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Pin Descriptions 2.2 Signal Definitions Table 2-2. Signal Definitions ( Signal Name I/O BCLK1 Bit Clock I (3) BCLK2 (3) BCLK3 QCLK1 Quaternary Clock I (3) QCLK2 (3) QCLK3 TDAT1 Transmit Data (3) TDAT2 (3) TDAT3 TAUX1 ...

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RS8953B/8953SPB HDSL Channel Unit Table 2-2. Signal Definitions ( Signal Name I/O TCLK Transmit Clock I RCLK Receive Clock EXCLK External Clock I TSER Transmit Serial I Data RSER Receive Serial Data TMSYNC Transmit I Multiframe Sync RMSYNC ...

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Pin Descriptions 2.2 Signal Definitions Table 2-2. Signal Definitions ( Signal Name I/O DROP Drop Indicator INSDAT Insert Data I INSERT Insert Indicator MCLK Master Clock SCLK System Clock VEXT External Voltage PLLVCC PLL Power PLLDGND PLL ...

Page 33

Circuit Descriptions 3.1 MPU Interface The Microprocessor Unit (MPU) interface consists of an 8-bit parallel multiplexed address-data bus, an associated bus control signal, and a maskable interrupt request output, as illustrated in interface is compatible with 8-bit processors running ...

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Circuit Descriptions 3.1 MPU Interface Figure 3-2. MPU Interrupt Logic Read IMR DATA Write IMR Read IRR Interrupt Event Write ICR 3.1.1 Address/Data Bus Address/data bus pins AD[7:0] allow MPU access to RS8953B internal registers. Read and write access ...

Page 35

RS8953B/8953SPB HDSL Channel Unit 3.1.3 Interrupt Request The open-drain interrupt request output (INTR*) indicates when a particular set of transmit, receive, or common status registers have been updated. Eight maskable interrupt sources are requested on the common INTR* pin: 1. ...

Page 36

Circuit Descriptions 3.2 PCM Channel 3.2 PCM Channel The Pulse Code Multiplexed (PCM) channel displayed in independent transmit and receive formatter circuits to control the flow of serial data between PCM and HDSL channels, to establish alignment between PCM ...

Page 37

RS8953B/8953SPB HDSL Channel Unit 3.2.1 PCM Transmit The PCM transmit formatter shown in serial data on the TSER and INSDAT inputs. Both inputs are sampled on the clock edge selected by TCLK_SEL [CMD_2; addr 0xE6] according to the format of ...

Page 38

Circuit Descriptions 3.2 PCM Channel Figure 3-5 when TFRAME_LOC is equal to 0. MSYNC with increasing bit and frame delays. NOTE: Figure 3-5. PCM Transmit Sync Timing TCLK TMSYNC MSYNC TSER INSDAT TCLK falling edge samples and rising edge ...

Page 39

RS8953B/8953SPB HDSL Channel Unit If the system does not apply PCM data aligned to MSYNC, then the application is asynchronously mapped, and the placement of timeslots, frames and multiframes is not aligned to HDSL payload bytes, blocks, or frames. Asynchronously ...

Page 40

Circuit Descriptions 3.2 PCM Channel 3.2.1.4 Drop/Insert PCM channels can carry timeslot data along a backplane that serves multiple Channel interfaces or subscriber line cards (see interface or line card be able to drop or insert individual PCM timeslots. ...

Page 41

RS8953B/8953SPB HDSL Channel Unit 3.2.1.5 TFIFO Water Each HDSL transmit channel aligns the start of its output frame with respect to Levels the PCM 6 ms sync according to the programmed TFIFO water level values [TFIFO_WL; addr 0x05]. PCM 6 ...

Page 42

Circuit Descriptions 3.2 PCM Channel 3.2.2 PCM Receive The PCM receive formatter shown in output according to receive combination table settings and the frame format defined by the PCM Formatter Registers (see operates on the clock edge selected by ...

Page 43

RS8953B/8953SPB HDSL Channel Unit Figure 3-10. PCM Receive Data Timing HDSL 6ms Master RFIFO_WL = PCM Bit Delay PCM 6ms RMSYNC RSER 0 X Bit RSER Frame 0 Frame RSER Mframe 0 Mframe RMSYNC can ...

Page 44

Circuit Descriptions 3.2 PCM Channel 3.2.2.1 Receive The Receive Multiframe Sync (RMSYNC) output can be programmed to mark Synchronization any bit position within the receive multiframe and does not affect RSER alignment with respect to the PCM 6 ms ...

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RS8953B/8953SPB HDSL Channel Unit 3.2.2.3 BER Meter PCM timeslots from TSER or RSER can be examined for test patterns on a per timeslot-basis, or the entire framed or unframed PCM channel from TSER can be examined (see PRBS_MODE in CMD_3; ...

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Circuit Descriptions 3.2 PCM Channel 3.2.2.4 RFIFO Water The RFIFO Water Level [RFIFO_WL; addr 0xCD] determines the PCM and Level HDSL receiver’s phase error tolerance and receive throughput data delay by establishing a fixed phase offset between the master ...

Page 47

RS8953B/8953SPB HDSL Channel Unit 3.3 Clock Recovery DPLL The Digital Phase Locked Loop (DPLL) shown in PCM Receive Clock (RCLK) from a 60–80 MHz High Frequency Clock (HFCLK). HFCLK is developed by analog PLL multiplication of the MCLK input frequency, ...

Page 48

Circuit Descriptions 3.3 Clock Recovery DPLL In closed loop operation, the Numerical Controlled Oscillator (NCO) synthesizes the nominal RCLK frequency according to the programmed HFCLK integer scale factor [DPLL_FACTOR; addr 0xD7] and the fractional scale factor [DPLL_RESID; addr 0xD5]. ...

Page 49

RS8953B/8953SPB HDSL Channel Unit 3.4 Loopbacks The RS8953B provides multiple PCM and HDSL loopbacks, as shown in Figure Loopback activation in the test direction does not disrupt the through data path in the non-test direction. Data path options (refer to ...

Page 50

Circuit Descriptions 3.4 Loopbacks Table 3-1. PCM And HDSL Loopbacks Loopback Command Register PP_LOOP CMD_2; addr 0xE6 HP_LOOP CMD_2; addr 0xE6 PH_LOOP RCMD_2; addr 0x61 PH_LOOP RCMD_2; addr 0x81 PH_LOOP RCMD_2; addr 0xA1 HH_LOOP TCMD_2; addr 0x07 HH_LOOP TCMD_2; ...

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RS8953B/8953SPB HDSL Channel Unit 3.5 HDSL Channel The three identical HDSL channels (CH1, CH2, and CH3) consist of separate transmit and receive circuits that are responsible for the assembly of HDSL output frames and the disassembly of HDSL receive frames. ...

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Circuit Descriptions 3.5 HDSL Channel Table 3-2. HDSL Frame Structure and Overhead Bit Allocation HOH Bit # 1–14 17–20 21–22 27–30 31–32 37–40 41–42 3-20 Symbol Bit Name sw1–sw14 SYNC word 15 losd Loss of Signal 16 febe Far ...

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RS8953B/8953SPB HDSL Channel Unit In T1 framing mode [E1_MODE = 0 in CMD_1; addr 0xE5], Z-bit positions are replaced by F-bits and are treated as payload with respect to the PCM channel. Figure 3-16 payload block contains 1 F-bit, plus ...

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Circuit Descriptions 3.5 HDSL Channel Figure 3-17. 2E1 Frame Format 72.5 = 870 YNC ORD ...

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RS8953B/8953SPB HDSL Channel Unit Table 3-3. HDSL Frame Mapping Examples Payload BYTE1 BYTE2 BYTE 3–35 BYTE36 BYTE37 BYTE 38–71 BYTE 72 BYTE 73–107 BYTE108 BYTE109–143 BYTE 144 N8953BDSB 2E1 VC- BYTES 32 BYTES R R ...

Page 56

Circuit Descriptions 3.5 HDSL Channel 3.5.1 HDSL Transmit Three identical HDSL transmitters accept data and sync from the PCM channel, insert HDSL overhead, and output serially encoded 2B1Q data on TDATn. One HDSL transmitter, shown in HOH multiplexer, STUFF ...

Page 57

RS8953B/8953SPB HDSL Channel Unit 3.5.1.3 CRC Calculation The Cyclic Redundancy Check (CRC) calculation is performed on all transmit data, and the HOH multiplexer inserts the resulting 6-bit CRC into the subsequent output frame. CRC is calculated over all bits in ...

Page 58

Circuit Descriptions 3.5 HDSL Channel The MPU can bypass the STUFF generator and select an alternate source of transmit STUFF bits by setting SLV_STUF [TCMD_2; addr 0x07] and selecting the alternate source in STUFF_SEL [CMD_5; addr 0xE9]. Alternate STUFF ...

Page 59

RS8953B/8953SPB HDSL Channel Unit 3.5.1.7 HDSL Auxiliary The HDSL auxiliary transmit channel provides an alternate source of HDSL Transmit payload bytes and optionally, an alternate source for the last 40 Z-bits transmitted in each HDSL frame. Auxiliary transmit data (TAUXn) ...

Page 60

Circuit Descriptions 3.5 HDSL Channel 3.5.2 HDSL Receive The RS8953B contains three identical HDSL receivers, each receiver the same as the one shown in destuffing, overhead extraction, descrambling of payload data, error performance monitoring, and payload mapping of HDSL ...

Page 61

RS8953B/8953SPB HDSL Channel Unit 3.5.2.2 HDSL Receive The HDSL receive framer acquires and maintains synchronization of the HDSL Framer channel and generates pointers that control overhead extraction in the STUFF, CRC and HOH demux circuitry. The MPU initializes the framer ...

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Circuit Descriptions 3.5 HDSL Channel After detecting a sync word and changing to the Sync Acquired state, the framer progresses through a programmable number of intermediate “Sync Acquired” states before entering the In Sync state. In each “Sync Acquired” ...

Page 63

RS8953B/8953SPB HDSL Channel Unit After entering In Sync, the framer either remains In Sync as successive sync words are detected, or regresses to the Sync Errored state if sync pattern errors are found. During Sync Errored states, the number of ...

Page 64

Circuit Descriptions 3.5 HDSL Channel 3.5.2.4 CRC Checking The Cyclic Redundancy Check (CRC) error is reported each time the calculated CRC of the (N)th HDSL frame does not match the CRC received in the (N+1)th HDSL frame. Individual block ...

Page 65

RS8953B/8953SPB HDSL Channel Unit Figure 3-26. HDSL Auxiliary Receive Z-bit Timing Payload Blocks ROH BCLK EOC0-3, CRC1-2, IND2-4, EOC4 RAUX ROH N8953BDSB Z13 Block ...

Page 66

Circuit Descriptions 3.6 PRA Function 3.6 PRA Function This document specifies requirements for using the integrated service digital network. Termination Equipment (TE) and the Exchange Termination (ET). Figure 3-27. An Overview of the PRA Transfer of Data RSER RMSYNC ...

Page 67

RS8953B/8953SPB HDSL Channel Unit Enabling the CRC4 generator causes CRC4 regeneration of the E1 data (RSER). The result is inserted into the data stream in the appropriate location in accordance with the CRC4 procedure specified in CCITT recommendation G.704. If ...

Page 68

Circuit Descriptions 3.6 PRA Function If CRC4 monitoring is disabled, new values must be inserted into the E-bits, or the E-bits must pass transparently (from the input TSER). If new values are inserted, these bits are obtained by enabling ...

Page 69

Registers All RS8953B registers are read-only or write-only. For registers that contain less than 8 bits, assigned bits reside in LSB positions; unassigned bits are ignored during write cycles and are indeterminate during read cycles. The LSB in ...

Page 70

Registers Register Types The Microprocessor Unit (MPU) must read and write real-time registers, and receive and transmit EOC, IND, Z-bit, and status registers within a prescribed time interval (1–6 ms) after their respective HDSL channel’ frame interrupt. ...

Page 71

RS8953B/8953SPB HDSL Channel Unit 4.1 Address Map The channel column (CHn) of Table 4-1 each register. Common registers are indicated by a ‘C’ in the CHn column. Table 4-1. Register Summary Address Map ( Addr CHn Write Register ...

Page 72

Registers 4.1 Address Map Table 4-1. Register Summary Address Map ( Addr CHn Write Register 0x1C — — 0x1D — — 0x1E — — 0x1F — — 0x20 2 TEOC_LO 0x21 2 TEOC_HI 0x22 2 TIND_LO 0x23 ...

Page 73

RS8953B/8953SPB HDSL Channel Unit Table 4-1. Register Summary Address Map ( Addr CHn Write Register 0x44 3 TZBIT_1 0x45 3 TFIFO_WL 0x46 3 TCMD_1 0x47 3 TCMD_2 0x48 3 TMAP_1 0x49 3 TMAP_2 0x4A 3 TMAP_3 0x4B 3 ...

Page 74

Registers 4.1 Address Map Table 4-1. Register Summary Address Map ( Addr CHn Write Register 0x82 2 RFIFO_RST 0x83 2 SYNC_RST 0x84 2 RMAP_1 0x85 2 RMAP_2 0x86 2 RMAP_3 0x87 2 ERR_RST 0x88 2 RSIG_LOC 0x89 ...

Page 75

RS8953B/8953SPB HDSL Channel Unit Table 4-1. Register Summary Address Map ( Addr CHn Write Register 0xC8 C FRAME_LEN_LO 0xC9 C FRAME_LEN_HI 0xCA C HFRAME_LEN_LO 0xCB C SYNC_WORD_A 0xCC C SYNC_WORD_B 0xCD C RFIFO_WL_LO 0xCE C RFIFO_WL_HI 0xCF C ...

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Registers 4.1 Address Map Table 4-1. Register Summary Address Map ( Addr CHn Write Register 0xEC C ICR 0xED C ROUTE_TBL 0xEE C COMBINE_TBL 0xEF C BER_RST 0xF0 C PRBS_RST 0xF1 C RX_RST 0xF2 C RSIG_TBL 0xF3 ...

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RS8953B/8953SPB HDSL Channel Unit 4.2 HDSL Transmit HDSL Channel 1 Base Address Table 4-2. HDSL Transmit Write Registers CH1 CH2 CH3 0x00 0x20 0x40 0x01 0x21 0x41 0x02 0x22 0x42 0x03 0x23 0x43 0x04 0x24 0x44 0xDF 0xE0 0xE1 0xE2 ...

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Registers 4.2 HDSL Transmit 0x00—Transmit Embedded Operations Channel (TEOC_LO 0x01—Transmit Embedded Operations Channel (TEOC_HI — — — The Transmit Embedded Operations Channel (TEOC) holds 13 EOC bits for transmission in TEOC[12:0] the next ...

Page 79

RS8953B/8953SPB HDSL Channel Unit 0xDF—Transmit Z-Bits (TZBIT_2 0xE0—Transmit Z-Bits (TZBIT_3 0xE1—Transmit Z-Bits (TZBIT_4 0xE2—Transmit Z-Bits (TZBIT_5 0xE3—Transmit Z-Bits (TZBIT_6 Transmit Z-bits is applicable only in ...

Page 80

Registers 4.2 HDSL Transmit TZBIT_1 is sampled on the respective transmit 6 ms frame interrupt, giving the MPU modify the TZBIT_1 contents for output in next frame. TZBIT_2 through TZBIT_6 are sampled during their ...

Page 81

RS8953B/8953SPB HDSL Channel Unit HDSL Overhead Enable—The HOH multiplexer inserts EOC, IND, and CRC bits. Otherwise, HOH_EN transmit overhead bits, except SYNC and STUFF, are forced to all 1s. HOH_EN = 0 select transmission of two-level or four-level scrambled 1s. ...

Page 82

Registers 4.2 HDSL Transmit Enable Repeater Mode—When set in both CH1 and CH2, REPEAT_EN cross-connects HDSL REPEAT_EN payload, SYNC, STUFF, and Z-bits from receive to transmit to implement a single pair repeater. REPEAT_EN has no effect in CH3. Transmit ...

Page 83

RS8953B/8953SPB HDSL Channel Unit 4.3 Transmit Payload Mapper The Transmit Payload Map (TMAP_1–TMAP_9) determines whether HDSL payload bytes (byte1 through byte36) are supplied from PCM timeslots, DBANK registers, or the HDSL auxiliary channel data. All routed timeslots to a given ...

Page 84

Registers 4.3 Transmit Payload Mapper 0x0F—Transmit Payload Map (TMAP_6 BYTE24 TMAP[1:0] BYTE23 TMAP[1:0] 0x10—Transmit Payload Map (TMAP_7 BYTE28 TMAP[1:0] BYTE27 TMAP[1:0] 0x11—Transmit Payload Map (TMAP_8 BYTE32 TMAP[1:0] BYTE31 TMAP[1:0] 0x12—Transmit ...

Page 85

RS8953B/8953SPB HDSL Channel Unit The following configurations can cause the HDSL frame to become corrupted: DBank_1, DBank_2, or DBank_3 is the source of data for HDSL payload byte #33. TFIFO or CBank_1 is the source of data for HDSL payload ...

Page 86

Registers 4.4 HDSL Receive 4.4 HDSL Receive HDSL Channel 1 Base Address Table 4-3. HDSL Receive Write Registers CH1 CH2 CH3 Register Label 0x60 0x80 0xA0 RCMD_1 0x61 0x81 0xA1 RCMD_2 0x62 0x82 0xA2 RFIFO_RST 0x63 0x83 0xA3 SYNC_RST ...

Page 87

RS8953B/8953SPB HDSL Channel Unit 0x60—Receive Command Register 1 (RCMD_1 FRAMER_EN[1:0] Reach Sync Framing Criteria—Contains the number of consecutive HDSL frames in which REACH_SYNC[2:0] the SYNC word is detected before the receive framer moves from the OUT_OF_SYNC to ...

Page 88

Registers 4.4 HDSL Receive 0x61—Receive Command Register 2 (RCMD_2 RX_ERR_EN PH_LOOP DSCR_EN SYNC Threshold Correlation—Upon the receive framer’s entry to a Sync Errored state, the THRESH_CORR[3:0] number of SYNC word locations searched is determined by the ...

Page 89

RS8953B/8953SPB HDSL Channel Unit Receive Error Interrupt Enable—Receive errors request RX_ERR interrupt and report RX_ERR_EN RXn_ERR status upon detection of RFIFO errors [STATUS_1; addr 0x05], framer state transitions or error counter overflows [STATUS_2; addr 0x06]. Disabled channels are prevented from ...

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Registers 4.5 Receive Payload Mapper 4.5 Receive Payload Mapper The Receive Payload Map (RMAP_1–RMAP_6) controls placement of HDSL payload bytes (byte1–byte36) into the RFIFO by instructing the mapper to place or discard payload bytes from the received payload block. ...

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RS8953B/8953SPB HDSL Channel Unit 0x6B—Receive Payload Map (RMAP_6 — — Receive Payload Map—Six registers hold a 36-bit value to define which of the received HDSL RMAP[35:0] payload bytes (byte1 through byte36) are placed into the RFIFO. RMAP[0] ...

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Registers 4.5 Receive Payload Mapper If RSIG_LOC is negative, then the programmed value equals 15. EOC messaging NOTE: capability may be used by the NTU to transfer the results of the RMSYNC phase measurement back to the LTU. Remote ...

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RS8953B/8953SPB HDSL Channel Unit 4.6 PCM Formatter Table 4-4. PCM Formatter Write Registers Address Register Label 0xC0 TFRAME_LOC_LO 0xC1 TFRAME_LOC_HI 0xC2 TMF_LOC 0xC3 RFRAME_LOC_LO 0xC4 RFRAME_LOC_LO 0xC5 RMF_LOC 0xC6 MF_LEN 0xC7 MF_CNT 0xC8 FRAME_LEN_LO 0xC9 FRAME_LEN_LO The PCM formatter supports ...

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Registers 4.6 PCM Formatter 0xC0—TSER Frame Bit Location (TFRAME_LOC_LO) TFRAME_LOC and TMF_LOC work in conjunction to define the location of bit 0, frame 0, at the TSER data input with respect to TMSYNC 0xC1—TSER Frame Bit ...

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RS8953B/8953SPB HDSL Channel Unit 0xC4—RSER Frame Bit Location (RFRAME_LOC_HI — — — RSER Frame Bit Location—Establishes the number of PCM bit delays, in the range of 1 bit to RFRAME_LOC[8:0] 512 bits, from the ...

Page 96

Registers 4.6 PCM Formatter PCM Multiframe Length—Contains the number of PCM frames in one PCM multiframe, in MF_LEN[5:0] the range frames. A value of zero selects one frame per multiframe, which causes TMSYNC and RMSYNC ...

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RS8953B/8953SPB HDSL Channel Unit 4.7 HDSL Channel Configuration Table 4-5. HDSL Channel Configuration Write Registers Address Register Label 0xCA HFRAME_LEN_LO 0xF5 HFRAME_LEN_HI 0xF8 HFRAME2_LEN_LO 0xF9 HFRAME2_LEN_HI 0xFA HFRAME3_LEN_LO 0XFB HFRAME3_LEN_HI 0xCB SYNC_WORD_A 0xCC SYNC_WORD_B 0xCD RFIFO_WL_LO 0xCE RFIFO_WL_HI 0xCF STF_THRESH_A_LO ...

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Registers 4.7 HDSL Channel Configuration 0xF5—HDSL Frame Length (HFRAME_LEN_HI — — — HDSL Payload Block Length—Contains the number of BCLKn bits, in the range 512, HFRAME_LEN[8:0] that are transmitted and received in an ...

Page 99

RS8953B/8953SPB HDSL Channel Unit 0xFB—HDSL Frame Length (HFRAME3_LEN_HI — — — HDSL Payload Block Length—Contains the number of BCLK3 bits, in the range 512, HFRAME3_LEN[8:0] that are transmitted and received in an HDSL payload ...

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Registers 4.8 Transmit Bit Stuffing Thresholds 0xCE—RX FIFO Water Level (RFIFO_WL_HI — — — Receive FIFO Water Level—Sets the RCLK bit delay from the master HDSL channel’s receive RFIFO_WL[8: frame to the PCM receive ...

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RS8953B/8953SPB HDSL Channel Unit where for STF_THRESH_A 0xCF—Bit Stuffing Threshold A (STF_THRESH_A_LO 0xD0—Bit Stuffing Threshold A (STF_THRESH_A_HI — — — Bit Stuffing Threshold A—Contains the number of GCLK cycles equaling 8 ...

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Registers 4.8 Transmit Bit Stuffing Thresholds 0xD4—Bit Stuffing Threshold C (STF_THRESH_C_HI — — — Bit Stuffing Threshold C—Contains the number of GCLK cycles equal to 24 HDSL bit times. STF_THRESH_C[8:0] If the phase measured from PCM ...

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RS8953B/8953SPB HDSL Channel Unit 4.9 DPLL Configuration Table 4-6. DPLL Configuration Write Registers Address Register Label 0xD5 DPLL_RESID_LO 0xD6 DPLL_RESID_HI 0xD7 DPLL_FACTOR 0xD8 DPLL_GAIN 0xDB DPLL_PINI 0xF6 DPLL_RST The DPLL synthesizes the PCM Receive Clock (RCLK) output from the 60 ...

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Registers 4.9 DPLL Configuration 0xD6—DPLL Residual (DPLL_RESID_HI DPLL Residual—Works in conjunction with DPLL_FACTOR to define the DPLL nominal DPLL_RESID[15:0] free-running frequency in Open Loop Mode or the DPLL initial frequency in Closed Loop Mode [DPLL_NCO in ...

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RS8953B/8953SPB HDSL Channel Unit 0xD8—DPLL Gain (DPLL_GAIN — DC_GAIN[2:0] DPLL Gain—Filtering is controlled by two DC parameters: DC_GAIN, which represents DPLL_GAIN[7:0] proportional loop gain, and DC_INTEG, which represents the filter’s integration coefficient. The DPLL closed loop bandwidth ...

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Registers 4.9 DPLL Configuration 0xDB—DPLL Phase Detector Init (DPLL_PINI DPLL Phase Detector Init (optional for RS8953B)—Phase detector init mode [PHD_MODE DPLL_PINI[7:0] in CMD_7; addr 0xF4] selects whether DPLL_PINI is supplied by the MPU or is calculated ...

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RS8953B/8953SPB HDSL Channel Unit 4.10 Data Path Options Table 4-7. Data Path Options Write Registers Address Register Label 0xDC DBANK_1 0xDD DBANK_2 0xDE DBANK_3 0xEA FILL_PATT 0xE4 TSTUFF 0xED ROUTE_TBL 0xEE COMBINE_TBL 0xF2 RSIG_TBL 0xDC—Data Bank Pattern 1 (DBANK_1) 7 ...

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Registers 4.10 Data Path Options The following configuration can cause the HDSL frame to become corrupted: DBank_1, DBank_2, or DBank_3 is the source of data for HDSL payload byte 33. DBank_2 is the source of data for HDSL payload ...

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RS8953B/8953SPB HDSL Channel Unit 0xED—Transmit Routing Table (ROUTE_TBL) MPU access to the transmit routing table’s single (ROUTE_TBL) register is enabled by first setting ROUTE_EN [CMD_3; addr 0xE7] to reset the table pointer. The MPU can then write ...

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Registers 4.10 Data Path Options Enable INSERT—Controls the state of the internal MUX and the INSERT output pin during INSERT_EN the corresponding PCM timeslot’s sample time. The next table entry is programmed to select the previous timeslot (ROUTE = ...

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RS8953B/8953SPB HDSL Channel Unit Data Bank Select (Applicable only if COMBINE = 00)—Selects one of three DBANK DBANK_SEL[1:0] registers to output on RSER during the respective timeslot. 0xF2—Receive Signaling Table (RSIG_TBL) Applicable only to the LTU grooming site in a ...

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Registers 4.11 Common Command 4.11 Common Command Table 4-8. Common Command Write Registers Address Register Label 0xE5 CMD_1 0xE6 CMD_2 0xE7 CMD_3 0xE8 CMD_4 0xE9 CMD_5 0xF3 CMD_6 0xF4 CMD_7 0xE5—Command Register 1 (CMD_1 E1_MODE PLL_DIS ...

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RS8953B/8953SPB HDSL Channel Unit 0xE6—Command Register 2 (CMD_2 GCLK_SEL PCM_FLOAT HP_LOOP PCM Transmit Clock Source—Selects which clock source and clock edge are used for PCM TCLK_SEL transmit inputs and outputs. PCM Receive Clock Source—Selects which clock source ...

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Registers 4.11 Common Command 0xE7—Command Register 3 (CMD_3 RSIG_WR PRBS_MODE[1:0] Enable Receive Combination Table Access—The write pointer for the combination table COMB_EN [COMBINE_TBL; addr 0xEE] is reset to 0, and table access is enabled. MPU writes ...

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RS8953B/8953SPB HDSL Channel Unit 0xE8—Command Register 4 (CMD_4) Must be set to 0x04 before any other MPU access to device, for normal operation. Other values are reserved for Conexant production test. 0xE9—Command Register 5 (CMD_5 DPLL_NCO MASTER_SEL[1:0] ...

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Registers 4.11 Common Command 0xF3—Command Register 6 (CMD_6 RAZ_[1:3] BER/PRBS Mode—Selects the BER meter source, the PRBS generator output direction, and BER_SEL[1:0] serial or framed data formats. Refer to MSYNC Phase Measurement—Selects whether TMSYNC or RMSYNC ...

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RS8953B/8953SPB HDSL Channel Unit 0xF4—Command Register 7 (CMD_7 PRA_EN FEBE_POLARITY NCO_SCALE DPLL Error Interrupt Enable—Enables DPLL errors to request RX_ERR interrupt when an DPLL_ERR_EN overflow or underflow condition occurs at the phase detector output. DPLL errors are ...

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Registers 4.11 Common Command NCO Scale Factor—Divides the NCO clock allow the NCO to synthesize the RCLK NCO_SCALE frequency at or below 128 kHz. GCLK and SCLK are not affected. Calculated values for DPLL_RESID [addr 0xD5] ...

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RS8953B/8953SPB HDSL Channel Unit 4.12 Interrupt and Reset Table 4-9. Interrupt and Reset Write Registers Address Register Label 0xEB IMR 0xEC ICR 0xEF BER_RST 0xF0 PRBS_RST 0xF1 RX_RST 0xEB—Interrupt Mask Register (IMR) The MPU writes IMR ...

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Registers 4.12 Interrupt and Reset 0xEF—Reset BER Meter/Start BER Measurement (BER_RST) Writing any data value to BER_RST clears the BER Meter error count [BER_METER; addr 0x1D]. The BER Meter Status [BER_STATUS; addr 0x1E] instructs the BER meter to begin ...

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RS8953B/8953SPB HDSL Channel Unit 4.13 Receive/Transmit Status HDSL Channel 1 (CH1) Base Address Table 4-10. Receive and Transmit Status Read Registers CH1 CH2 CH3 Register Label 0x00 0x08 0x10 REOC_LO 0x01 0x09 0x11 REOC_HI 0x02 0x0A 0x12 RIND_LO 0x03 0x0B ...

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Registers 4.13 Receive/Transmit Status 0x01—Receive Embedded Operations Channel (REOC_HI MFG[2:0] Receive EOC—Holds 13 EOC bits received during the previous HDSL frame. Refer to REOC[12:0] Table 3-2 (Overhead Bit Allocation) for EOC bit positions within the frame. ...

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RS8953B/8953SPB HDSL Channel Unit 0x18—Receive Z-Bits (RZBIT_2 0x19—Receive Z-Bits (RZBIT_3 0x1A—Receive Z-Bits (RZBIT_4 0x1B—Receive Z-Bits (RZBIT_5 0x1C—Receive Z-Bits (RZBIT_6 Receive Z-bits—Applicable only in E1_MODE [CMD_1; ...

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Registers 4.13 Receive/Transmit Status SYNC_WORD_A or SYNC_WORD_B Acquired—Reports which one of the two SYNC_AB programmed SYNC words is detected by the receive framer. Updated each time the receive framer state transitions from OUT_OF_SYNC to SYNC_ACQUIRED. Tip/Ring Inversion—Indicates the receive ...

Page 125

RS8953B/8953SPB HDSL Channel Unit 0x06—Receive Status 2 (STATUS_2 FEBE_OVR CRC_OVR CRC_ERR Intermediate State Count—Applicable only if SYNC_STATE reports SYNC_ACQUIRED or STATE_CNT[2:0] SYNC_ERRORED states. STATE_CNT indicates the framer’s progress through the intermediate states. Receive Framer Synchronization State—Reports the ...

Page 126

Registers 4.13 Receive/Transmit Status 0x07—Transmit Status (STATUS_3 — — — Transmit STUFF Decision—Indicates whether the last transmitted HDSL frame was output TX_STUFF with 4 STUFF bits or none. Transmit FIFO Full Error—Indicates the TFIFO has overflowed. ...

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RS8953B/8953SPB HDSL Channel Unit CRC Error Count—Indicates the total number of received CRC errors detected by the receive CRC_CNT[7:0] framer, and increments by one for each received HDSL 6 ms frame that contains CRC_ERR [STATUS_1; addr 0x06]. CRC_CNT is cleared ...

Page 128

Registers 4.14 Common Status 4.14 Common Status Table 4-11. Common Status Read Registers Address Register Label Bits 0x1D BER_METER 0x1E BER_STATUS 0x1F IRR 0x20 RESID_OUT_HI 0x28 RESID_OUT_LO 0x30 IMR 0x38 PHS_ERR 0x39 MSYNC_PHS_LO 0x3A MSYNC_PHS_HI 0x3B SHADOW_WR 0x3C ERR_STATUS ...

Page 129

RS8953B/8953SPB HDSL Channel Unit 0x1E—BER Status (BER_STATUS — — — BER Pattern SYNC—Applicable only if SYNC_DONE is active. BER_SYNC reports BER_SYNC whether the BER meter acquired test pattern sync during the 128-bit test pattern qualification period. The ...

Page 130

Registers 4.14 Common Status Receive HDSL 6 ms Frame Interrupt—Reported coincident with the start of the receive 6 ms RX1-RX3 frame for the respective HDSL channel. This allows the MPU to synchronize read access of the real time receive ...

Page 131

RS8953B/8953SPB HDSL Channel Unit 0x38—DPLL Phase Error (PHS_ERR DPLL Phase Error—The DPLL phase detector error output is given in 2’s complement format PHS_ERR[7:0] in units of GCLK cycles, where minimum (negative) phase is reported as 0x80 and ...

Page 132

Registers 4.14 Common Status The NTU in a P2MP application uses both measurements to monitor the phase difference between incoming and outgoing HDSL frames, to adjust its output frame location accordingly to align with other remote sites, and to ...

Page 133

RS8953B/8953SPB HDSL Channel Unit 4.15 PRA Transmit Read Table 4-12. PRA Transmit Read Registers Address Register Label 0x40 TX_PRA_CTRL0 0x41 TX_PRA_CTRL1 0x42 TX_PRA_MON1 0x43 TX_PRA_E_CNT 0x45 TX_PRA_CODE 0x46 TX_PRA_MON0 0x47 TX_PRA_MON2 0x40—PRA Transmit Control Register 0 (TX_PRA_CTRL0 ...

Page 134

Registers 4.15 PRA Transmit Read Controls the behavior of Sa7 bits, transmitted towards the HDSL link, as follows: SA7_MODE Controls the behavior of Sa8 bits transmitted towards the HDSL link, as follows: SA8_MODE Controls the behavior of the E-bits ...

Page 135

RS8953B/8953SPB HDSL Channel Unit Enables to override all 32 slots of an PCM frame except Slot 0, transmitted towards the HDSL AIS link, with a constant pattern: AIS enables to achieve framed AIS. To achieve unframed arbitrary AUX pattern NOTE: ...

Page 136

Registers 4.15 PRA Transmit Read This register is updated once every PCM multiframe. The bits in this register correspond to the bits in the transmitted PCM multiframe stream, in the PCM to HDSL direction. Sa6 _1, _2, _3, _4 ...

Page 137

RS8953B/8953SPB HDSL Channel Unit 4.16 PRA Transmit Write Table 4-13. PRA Transmit Write Registers Address Register Label 0x70 TX_PRA_CTRL0 0x71 TX_PRA_CTRL1 0x72 TX_BITS_BUFF1 0x73 TX_PRA_TMSYNC_OFFSET 0x74 TX_BITS_BUFFO 0x70—PRA Transmit Control Register 0 (TX_PRA_CTRL0 E_MODE[1:0] SA8_MODE Controls the ...

Page 138

Registers 4.16 PRA Transmit Write Controls the behavior of Sa8 bits, transmitted towards the HDSL link, as follows: SA8_MODE Controls the behavior of the E-bits transmitted towards the HDSL link, as follows: E_MODE The Automatic mode operates in conjunction ...

Page 139

RS8953B/8953SPB HDSL Channel Unit Enables to override all 32 slots of an PCM frame except slot 0 transmitted towards the HDSL AIS link, with a constant pattern: AIS enables to achieve framed AIS. To achieve unframed arbitrary AUX pattern NOTE: ...

Page 140

Registers 4.16 PRA Transmit Write When this assumption is not valid, this register may be used to internally reposition the TMSYNC to coincide with Bit 0. 0x74—PRA Transmit Bits Buffer 0 (TX_BITS_BUFF0 ...

Page 141

RS8953B/8953SPB HDSL Channel Unit 4.17 PRA Receive Read Table 4-14. PRA Receive Read Registers Address Register Label 0x80 RX_PRA_CTRL0 0x81 RX_PRA_CTRL1 0x82 RX_BITS_BUFF1 0x83 RX_PRA_E_CNT 0x84 RX_PRA_CRC_CNT 0x85 RX_PRA_CODE 0x86 RX_PRA_MON0 0x87 RX_PRA_MON2 0x80—PRA Receive Control Register 0 (RX_PRA_CTRL0) 7 ...

Page 142

Registers 4.17 PRA Receive Read Controls the behavior of the E-bits transmitted towards the HDSL link, as follows: E_MODE The Automatic mode works in conjunction with the transmitter CRC4 check result (reported also in TX_PRA_MON0), as follows: The value ...

Page 143

RS8953B/8953SPB HDSL Channel Unit Clears the RX_E counter, as follows: RST_E_CNT Clears the RX_CRC counter, as follows: RST_CRC_CNT The value of this register takes effect starting with the next PCM multiframe NOTE: following the write access cycle completion. 0x82—PRA Receive ...

Page 144

Registers 4.17 PRA Receive Read The register is updated twice each PCM multiframe. It increments each time a mismatch between the reported and calculated CRC4 is detected. The counter wraps around at 255 cleared/enabled by RESET_CRC_CNT of ...

Page 145

RS8953B/8953SPB HDSL Channel Unit 4.18 PRA Receive Write Table 4-15. PRA Receive Write Registers Address Register Label 0xB0 RX_PRA_CTRL0 0xB1 RX_PRA_CTRL1 0xB2 RX_BITS_BUFF1 0xB4 RX_PRA_BUFF0 0xB0—PRA Receive Control Register 0 (RX_PRA_CTRL0 E_MODE[1:0] SA8_MODE Controls the behavior of ...

Page 146

Registers 4.18 PRA Receive Write The Automatic mode operates in conjunction with the transmitter CRC4 check result (reported also in TX_PRA_MON0), as follows: The value of this register takes effect starting with the next PCM multiframe NOTE: following the ...

Page 147

RS8953B/8953SPB HDSL Channel Unit Clears the RX_CRC counter, as follows: RST_CRC_CNT The value of this register takes effect starting with the next PCM multiframe, NOTE: following the write access cycle completion. 0xB2—PRA Receive Bits Buffer 1 (RX_BITS_BUFF1 ...

Page 148

Registers 4.18 PRA Receive Write The new value to be inserted into the direction used in all odd frames. 5 The new value to be inserted into the Sa Sa _1, _2, _3, _4 ...

Page 149

Applications The following chapter shows typical interconnections of the RS8953B HDSL channel unit: • Conexant HDSL Transceiver • Bt8370 E1/T1 Primary Rate Framer • Motorola 68302 16-bit Processor • Intel 8051 8-bit Processor N8953BDSB 5 Conexant 5-1 ...

Page 150

Applications 5.1 Interfacing to a Conexant HDSL Transceiver 5.1 Interfacing to a Conexant HDSL Transceiver Figure 5-1 channel unit and a Conexant HDSL transceiver. Figure 5-1. RS8953B HDSL Channel Unit to Conexant HDSL Transceiver Interconnection TDAT1 QCLK1 RDAT1 BCLK1 ...

Page 151

RS8953B/8953SPB HDSL Channel Unit 5.2 Interfacing to the Bt8370 E1/T1 Framer Figure 5-2 channel unit and the Bt8370 E1/T1 framer. Figure 5-2. RS8953B HDSL Channel Unit to Bt8360 DS1 Framer Interconnection RSBCKI/RCKO Bt8370 TSBCKI/TCKI N8953BDSB illustrates a typical interconnection between ...

Page 152

Applications 5.3 Interfacing to the 68302 Processor 5.3 Interfacing to the 68302 Processor Figure 5-3 channel unit and the 68302 processor. Figure 5-3. RS8953B to 68302 Processor Interconnection A[15] AS MC68302 DS R/W A[7:0] D[7:0] IRQ6 5-4 illustrates a ...

Page 153

RS8953B/8953SPB HDSL Channel Unit 5.4 Interfacing to the 8051 Controller Figure 5-4 channel unit and the 8051 controller. Figure 5-4. RS8953B HDSL Channel Unit to 8051 Controller Interconnection 8051 AD[15] AD[7:0] INT0 N8953BDSB illustrates a typical interconnection between the RS8953B ...

Page 154

Applications 5.5 References 5.5 References Applicable specifications: • Bellcore TA-NWT-001210 • Bellcore FA-NWT-001211 • ETSI RTR/TM–03036 • CCITT Recommendation G.704 • Bellcore TR-NWT-000499 5-6 Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...

Page 155

Electrical and Timing Specifications 6.1 Absolute Maximum Ratings Table 6-1. Absolute Maximum Ratings Symbol Parameter VCC Supply Voltage V Voltage on Any Signal Pin I T Storage Temperature ST T Vapor Phase Soldering VSOL Temperature (1 minute) Thermal Resistance ...

Page 156

Electrical and Timing Specifications 6.1 Absolute Maximum Ratings 6.1.2 Electrical Characteristics Table 6-3. Electrical Characteristics Symbol Parameter I Supply Current CC PCM = 4.096 Mbps HDSL = 2.320 Mbps Supply Current 1T1 Supply Current 2T1 Supply Current 1E1 Supply ...

Page 157

RS8953B/8953SPB HDSL Channel Unit 6.1.3 Timing Requirements Figure 6-1. Input Clock Timing Input Clock Table 6-4. Clock Timing Requirements Symbol Parameter 1/ Tp Mclk Frequency (Pll_dis = 0; Pll_mul = 16) Mclk Frequency (Pll_dis = 0; Pll_mul = 8) Mclk ...

Page 158

Electrical and Timing Specifications 6.1 Absolute Maximum Ratings Table 6-5. Data Timing Requirements Symbol Parameter Ts Input Setup Time Thld Input Hold Time Table 6-6. Input Clock Edge Selection Clock Edge BCLK1 Falling BCLK2 Falling BCLK3 Falling TCLK Falling ...

Page 159

RS8953B/8953SPB HDSL Channel Unit 6.1.4 Switching Characteristics Figure 6-3. Output Clock and Data Timing Output Clock Falling Edge Outputs Thld Rising Edge Outputs Table 6-7. Clock and Data Switching Characteristics Symbol Parameter 1/Tp SCLK Frequency RCLK Frequency Th Clock Width ...

Page 160

Electrical and Timing Specifications 6.1 Absolute Maximum Ratings Table 6-8. Output Clock Edge Selection Clock Edge BCLK1 Rising TDAT1, TLOAD1, RAUX1, ROH1 BCLK2 Rising TDAT2, TLOAD2, RAUX2, ROH2 BCLK3 Rising TDAT3, TLOAD3, RAUX3, ROH3 TCLK Rising TCLK Falling RCLK ...

Page 161

RS8953B/8953SPB HDSL Channel Unit 6.1.5 MPU Interface Timing Motorola- (MPUSEL = 1) and Intel- (MPUSEL = 0) style microprocessor bus timing, as follows: Table 6-9. MPU Interface Timing Requirements Symbol Parameter 1 ALE Pulse-Width High 2 Address Input Setup to ...

Page 162

Electrical and Timing Specifications 6.1 Absolute Maximum Ratings Figure 6-4. MPU Write Timing, MPUSEL = 1 ALE AD[7:0] CS* RD* (Data Strobe) WR* (Write Enable) INTR* Figure 6-5. MPU Read Timing, MPUSEL = 1 ALE AD[7:0] RD* CS* WR* ...

Page 163

RS8953B/8953SPB HDSL Channel Unit Figure 6-6. MPU Write Timing, MPUSEL = 0 ALE 1 2 AD[7:0] WR* CS* INTR* Figure 6-7. MPU Read Timing, MPUSEL = 0 ALE 1 2 AD[7:0] RD* CS* N8953BDSB 3 ADDRESS DATA INPUT 5 6 ...

Page 164

Electrical and Timing Specifications 6.2 Mechanical Specifications 6.2 Mechanical Specifications Figure 6-8. 68-Pin PLCC Package Drawing 6-10 Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...

Page 165

RS8953B/8953SPB HDSL Channel Unit Figure 6-9. 80–Pin PQFP Mechanical Specification N8953BDSB 6.0 Electrical and Timing Specifications 6.2 Mechanical Specifications Conexant 6-11 ...

Page 166

Electrical and Timing Specifications 6.2 Mechanical Specifications 6-12 Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...

Page 167

Acronyms, Abbreviations and Notation 7.1 Arithmetic Notation 7.1.1 Bit Numbering The Least Significant Bit (LSB) having the lowest number represents the lowest number within a bit. 7.1.2 Acronyms and Abbreviations N8953BDSB 7 AIS Alarm Indication Signal 2B1Q 2 Binary, ...

Page 168

Acronyms, Abbreviations and Notation 7.1 Arithmetic Notation 7-2 VCXO Voltage-Controlled Crystal Oscillator Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...

Page 169

Appendix A A.1 Differences Between Bt8953A and RS8953B Table A-1. Pin Definitions Pin Number 68 Pin 80 Pin Signal PLCC PQFP 19 13 VCC 27 23 VCC 48 48 PLLVCC 49 49 VCC (SCAN_MD VCC 44 43 LP1 ...

Page 170

Appendix A A.1 Differences Between Bt8953A and RS8953B Table A-2. Power Consumption Configuration Maximum 528 Kbps on single DSL / 2.048 Mbps on PCM 1040 Kbps on single DSL / 2.048 Mbps on PCM 1168 Kbps on single DSL / ...

Page 171

Appendix B: Bt8953A/RS8953B Product Bulletin B.1 BCLK Phase Constraints In Repeater Mode; Non-Conformance Product Affected: Bt8953A and RS8953B While in repeater mode (REPEAT_EN = 1 for CH1 and CH2), a BCLK1 to BCLK2 phase difference of 180 degrees, +/- 5 ...

Page 172

Appendix B : Bt8953A/RS8953B Product Bulletin B.1 BCLK Phase Constraints In Repeater Mode; Non-Conformance Product Affected: Bt8953A and RS8953B HCLK BCLK BCLK1 QCLK QCLK1 TDAT TDAT1 RDAT RDAT1 HTU-R Bt8953A/RS8953B Zipwire Transceiver B-2 1 CLK D 0 MCLK BCLK2 0 ...

Page 173

... Phone: (852) 2827 0181 Fax: (852) 2827 6488 Web Site www.conexant.com India Phone: (91 11) 692 4780 Fax: (91 11) 692 4712 World Headquarters Conexant Systems, Inc. 4311 Jamboree Road Korea P. O. Box C Phone: (82 2) 565 2880 Newport Beach, CA Fax: (82 2) 565 1440 92658-8902 ...

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