BT8376EPF Conexant Systems, Inc., BT8376EPF Datasheet

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BT8376EPF

Manufacturer Part Number
BT8376EPF
Description
Fully integrated T1/E1 framer and line interface
Manufacturer
Conexant Systems, Inc.
Datasheet

Specifications of BT8376EPF

Case
QFP
Dc
00+/01+

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Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
The Bt8370/8375/8376 is a family of single chip transceivers for T1/E1 and Integrated
Service Digital Network (ISDN) primary rate interfaces, operating at 1.544 Mbps or
2.048 Mbps. These devices combine a sophisticated framer, transmit and receive slip
buffers, and an on-chip physical line interface to provide a complete T1/E1 transceiver.
programmable clock rate adapter for simplifying system bus interfacing. The adapter
synthesizes standard clock signals from the receive or transmit line rate clocks or from an
external reference.
microprocessor port. Current ANSI, ETSI, ITU-T, and Bellcore standards are supported for
alarm and error monitoring, signaling supervision (e.g., LAPD/SS7), per-channel trunk
conditioning, and Facility Data Link (FDL) maintenance. A serial Time Division Multiplexed
(TDM) system bus interface allows the backplane Pulse Code Modulation (PCM) data
highway to operate at rates from 1.536 to 8.192 Mbps. Extensive test and diagnostic
functions include a full set of digital and analog loopbacks, PRBS test pattern generation,
BER meter, and forced error insertion.
The physical line interface circuit recovers clock and data from analog signals with +3 to
–43 dB cable attenuation, appropriate for both short (–18 dB) and long-haul T1/E1
applications. Receive line equalization (EQ) and transmit Line Build Out (LBO) filters are
implemented using Digital Signal Processor (DSP) circuits for reliable performance. Data
and/or clock jitter attenuation can be inserted on either the receive or transmit path. The
transmit section includes precision pulse shaping and amplitude pre-emphasis for cross
connect applications, as well as a set of LBO filters for long-haul Channel Service Unit
(CSU) applications. A complementary driver output is provided to couple 75/100/120
lines via an external transformer.
Functional Block Diagram
Data Sheet
Transmit
Receive
Analog
Analog
The fully featured Bt8370 and short-haul Bt8375 and Bt8376 devices provide a
Operations are controlled through memory-mapped registers accessible via a parallel
RX
Test Port
RPLL
TPLL
JTAG
TX
Pulse
LBO
EQ
Processor Bus
Control/Status
Motorola/Intel
Registers
Attenuator
TX or RX
Jitter
Data Link Controllers
Dual-Rail/NRZ/
Decode
Encode
External DL3
ZCS
ZCS
DL1 + DL2
Overhead
Receive
Insertion
Framer
T1/E1
Clock Rate
CLAD I/O
Adaptor
Transmit
Buffer
Buffer
Framer
Slip
T1/E1
RX
Slip
TX
Receive
System
Bus
Transmit
System
Bus
Distinguishing Features
• Single-chip T1/E1 framer with
• Frames to popular T1/E1 standards:
• On-chip physical line interface
• Two-frame transmit and receive PCM
• Clock rate adapter synthesizes jitter
• Parallel 8-bit microprocessor port
• Automated Facility Data Link (FDL)
• BERT generation and counting
• Two full-duplex HDLC controllers for
• B8ZS/HDB3/Bit 7 zero suppression
• 80-pin MQFP surface-mount package
• Operates from a single +5 Vdc ±5%
• Low-power CMOS technology
Applications
• T1/E1 Channel Service Unit/Data
• Digital Access Cross-Connect
• T1/E1 Multiplexer (MUX)
• PBXs and PCM channel bank
• T1/E1 HDSL terminal unit
• ISDN Primary Rate Access (PRA)
short/long-haul physical line
interface
– T1: SF, ESF, SLC 96, T1DM
– E1: PCM
compatible with:
– DSX-1/E1 short-haul signals
– DS-1 (T1.403) and ETSI long-haul
slip buffers
attenuated system clocks from an
internal or external reference
supports Intel or Motorola buses
management
data link and LAPD/SS7 signaling
power supply
Service Unit (CSU/DSU)
Systems (DACS)
ISDN primary rate
signals
-
30, G.704, G.706, G.732
June 30, 1999
N8370DSE

Related parts for BT8376EPF

BT8376EPF Summary of contents

Page 1

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface The Bt8370/8375/8376 is a family of single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces, operating at 1.544 Mbps or 2.048 Mbps. These devices combine a sophisticated ...

Page 2

... MQFP Bt8370KPF 80-Pin MQFP Bt8375EPF 80-Pin MQFP Bt8375KPF 80-Pin MQFP Bt8376EPF 80-Pin MQFP Bt8376KPF 80-Pin MQFP NOTE(S): (1) Cost reduced Bt8375 and Bt8376 are pin and register-compatible versions of Bt8370 with reduced features. Contact the local sales representative for ordering information and pricing. ...

Page 3

Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

Table of Contents 2.4.5 Alarm Monitor 2.4.5.1 Loss of Frame 2.4.5.2 Loss of Signal 2.4.5.3 Analog Loss of Signal 2.4.5.4 Alarm Indication Signal 2.4.5.5 Yellow Alarm 2.4.5.6 Multiframe YEL 2.4.5.7 Severely Errored Frame 2.4.5.8 Change of Frame Alignment 2.4.5.9 Receive ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.8.5 Test Pattern Generator 2.8.6 Transmit Error Insertion 2.8.7 In-Band Loopback Code Generator 2.8.8 ZCS Encoder 2.9 Transmit Line Interface Unit . . . . . . . . . . . ...

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Table of Contents 3.0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 3.7 Receive LIU Registers 020—LIU Configuration (LIU_CR) 021—Receive LIU Status (RSTAT) 022—Receive LIU Configuration (RLIU_CR) 023—RPLL Low Pass Filter (LPF) 024—Variable Gain Amplifier Maximum (VGA_MAX) 025—Equalizer Coefficient Data Register (EQ_DAT) 026—Equalizer Coefficient ...

Page 8

Table of Contents 3.11 Transmit LIU Registers 060–067—Transmit Pulse Shape Configuration (SHAPE) 068—Transmit LIU Configuration (TLIU_CR) 3.12 Transmitter Registers 070—Transmit Framer Configuration (TCR0) 071—Transmitter Configuration (TCR1) 072—Transmit Frame Format (TFRM) 073—Transmit Error Insert (TERROR) 074—Transmit Manual Sa-Byte/FEBE Configuration (TMAN) 075—Transmit ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 0B0—DL2 Bit Enable (DL2_BIT) 0B1—DL2 Control (DL2_CTL) 0B2—RDL #2 FIFO Fill Control (RDL2_FFC) 0B3—Receive Data Link FIFO #2 (RDL2) 0B4—RDL #2 Status (RDL2_STAT) 0B6—TDL #2 FIFO Empty Control (TDL2_FEC) 0B7—TDL #2 End ...

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Table of Contents 4.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface List of Figures Figure 1-1. Bt8370/8375/8376 Pinout Diagram ...

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List of Figures Figure 2-38. E1 (G.703) Pulse Template Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface List of Tables Table 1-1. Hardware Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 14

List of Tables Table 3-11. Receive PRBS Test Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Table 5-16. Intel Synchronous Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 16

List of Tables xvi Fully Integrated T1/E1 Framer and Line Interface Conexant Bt8370/8375/8376 N8370DSE ...

Page 17

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 1 1.0 Pin Descriptions 1.1 Pin Assignments Bt8370/8375/8376 is packaged in an 80-pin Metric Quad Flat Pack (MQFP). A pinout diagram of this device is illustrated in Bt8370/8375/8376 logic diagram. Pin labels, ...

Page 18

Pin Descriptions 1.1 Pin Assignments Figure 1-1. Bt8370/8375/8376 Pinout Diagram SYNCMD 1 CS* 2 INTR* 3 DS* (RD AS* (ALE) R/W*(WR*) 6 VDD[0] 7 GND[0] 8 A[0] 9 AD[0] 10 A[1] 11 AD[1] 12 A[2] 13 AD[2] ...

Page 19

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Figure 1-2. Bt8370/8375/8376 Logic Diagram 28 Hardware Reset I 29 Processor Clock I 78 Motorola Bus mode I 1 Sync Bus mode I 26 Clock mode I (1) Address Bus I (1) ...

Page 20

Pin Descriptions 1.1 Pin Assignments Table 1-1. Hardware Signal Definitions ( Pin Label Signal Name RST* Hardware Reset MCLK Processor Clock MOTO* Motorola Bus mode SYNCMD Sync mode CLKMD Clock mode A[8:0] Address Bus AD[7:0] Data Bus ...

Page 21

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Table 1-1. Hardware Signal Definitions ( Pin Label Signal Name Microprocessor Interface (MPU) (Continued) ONESEC 1-second Timer INTR* Interrupt Request DTACK* Data Transfer Acknowledge XOE Transmit Output Enable RTIP, RRING ...

Page 22

Pin Descriptions 1.1 Pin Assignments Table 1-1. Hardware Signal Definitions ( Pin Label Signal Name TPOSI TX Positive Rail Input TNEGI TX Negative Rail Input TPOSO TX Positive Rail Output TNEGO TX Negative Rail Output TDLI TX ...

Page 23

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Table 1-1. Hardware Signal Definitions ( Pin Label Signal Name RCKI RX Clock Input RPOSI RX Positive Rail Input RNEGI RX Negative Rail Input RCKO RX Clock Output RPOSO RX ...

Page 24

Pin Descriptions 1.1 Pin Assignments Table 1-1. Hardware Signal Definitions ( Pin Label Signal Name TSBCKI TSB Clock Input TPCMI TSB Data Input TSIGI TSB Signaling Input TINDO TSB Time Slot Indicator TFSYNC TSB Frame Sync TMSYNC ...

Page 25

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Table 1-1. Hardware Signal Definitions ( Pin Label Signal Name RSBCKI RSB Clock Input RPCMO RSB Data Output RSIGO RSB Signaling Output RINDO RSB Time Slot Indicator RFSYNC RSB Frame ...

Page 26

Pin Descriptions 1.1 Pin Assignments Table 1-1. Hardware Signal Definitions ( Pin Label Signal Name SIGFRZ Signaling Freeze NOTE(S): 1. All RSB and TSB outputs can be placed in high-impedance state (see SBI_OE; addr 0D0). 2. Receive ...

Page 27

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Table 1-1. Hardware Signal Definitions ( Pin Label Signal Name CLADI CLAD Input REFCKI Reference Clock CLADO CLAD Output TDI JTAG Test Data Input TMS JTAG Test mode Select TDO ...

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Pin Descriptions 1.1 Pin Assignments 1-12 Fully Integrated T1/E1 Framer and Line Interface Conexant Bt8370/8375/8376 N8370DSE ...

Page 29

Circuit Description 2.1 Bt8370/8375/8376 Block Diagrams Detailed block diagrams are illustrated in (Bt8375), and block diagrams, along with descriptions, appear throughout this section. 1. Receive Line Interface Unit (RLIU) 2. Jitter Attenuator (JAT) 3. Digital Receiver (RCVR) 4. Receive ...

Page 30

RPOSI RNEGI RCKI Data Slicer RPLL AGC RTIP 0 RRING Adaptive VGA ADC Equalizer 1 AIS 1 LBO Pulse XTIP DAC DRV Filters Shape XRING 0 8X TPLL XOE TPOSO TNEGO TCKO Microprocessor Port External DLINK PRBS/Inband LB DLINK 2 ...

Page 31

RPOSI RNEGI RCKI Data Slicer RPLL AGC RTIP 0 RRING Adaptive VGA ADC Equalizer 1 1 AIS Pulse XTIP DAC DRV Shape XRING 0 8X TPLL XOE TPOSO TNEGO TCKO Microprocessor Port External DLINK PRBS/Inband LB DLINK 2 Buffer 1 ...

Page 32

RPOSI RNEGI RCKI Data Slicer RPLL AGC RTIP 0 RRING Adaptive VGA ADC Equalizer 1 1 AIS Pulse XTIP DAC DRV Shape XRING 0 8X TPLL XOE TPOSO TNEGO TCKO Microprocessor Port External DLINK PRBS/Inband LB 1 DLINK 1 Buffer ...

Page 33

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.2 Receive Line Interface Unit The Receive Line Interface Unit (RLIU) recovers clock and data from the bipolar Alternate Mark Inversion (AMI) line signal that has been attenuated and distorted due to ...

Page 34

Circuit Description 2.2 Receive Line Interface Unit Figure 2-5. RLIU Waveforms—Bipolar Input Signal RTIP , 1 3 RRING 2 RXCLK 1 RPOSO RNEGO If the RLIU functionality is not required, a bypass mode is provided [RDIGI; addr 020]. If ...

Page 35

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.2.1 Data Recovery The RLIU recovers data from the received analog signal by normalizing the signal with the Variable Gain Amplifier (VGA) and the Automatic Gain Control (AGC), removing distortion with the ...

Page 36

Circuit Description 2.2 Receive Line Interface Unit 2.2.2 Clock Recovery 2.2.2.1 Phase Locked The Receive Phase Locked Loop (RPLL) recovers the line rate clock from the Loop Data Slicer dual rail outputs. The RPLL generates a recovered clock that ...

Page 37

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.3 Jitter Attenuator The Jitter Attenuator (JAT), illustrated in receive or transmit path, but not both simultaneously. In the receive configuration, the line signal is recovered by the RLIU and is dejittered ...

Page 38

Circuit Description 2.3 Jitter Attenuator 2.3.1 Elastic Store The elastic store size (RJAT or TJAT) is configurable using JSIZE[2:0] in the JAT_CR. The elastic store sizes available are 8, 16, 32, 64, and 128 bits. The 32-bit elastic store ...

Page 39

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Figure 2-9. CLAD/JAT Input Jitter Tolerance 10.0 k 1.0 k 138 UI 100.0 ITU-T 10.0 Rec G.824 (T1) 7.70 4.88 ITU-T Rec G.823 (E1) 1.0 0.1 0.1 1.0 N8370DSE ...

Page 40

Circuit Description 2.3 Jitter Attenuator Figure 2-10. CLAD/JAT Jitter Transfer Functions 0 -10 -20 -30 -40 (Max. Attn. Boundary) -50 -60 1 2-12 Fully Integrated T1/E1 Framer and Line Interface (Min. Atten. Boundary) TR 62411 (Min. Atten. Boundary) TR ...

Page 41

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Table 2-1. CLAD/JAT Jitter Transfer Functions Curve N8370DSE JAT FIFO Size (bits) A 128 0x06 B 128 0x05 64 0x06 C 128 0x04 64 0x05 32 0x06 D 64 0x04 32 0x05 ...

Page 42

Circuit Description 2.4 Receiver 2.4 Receiver The Digital Receiver (RCVR) monitors T1/E1 overhead data and decodes positive and negative rail NRZ data from the RLIU into single rail NRZ data processed by the RSB. The RCVR, illustrated in following ...

Page 43

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.4.1 ZCS Decoder The Receive Zero Code Suppression (RZCS) decoder decodes the dual rail data (bipolar) into single rail data (unipolar). The Receive AMI bit (RAMI) in the Receiver Configuration register [RCR0; ...

Page 44

Circuit Description 2.4 Receiver 2.4.3 Error Counters The following Performance Monitoring (PM) counters are available in the RCVR: Framing Bit Errors (FERR), CRC Errors (CERR), Line Code Violations (LCV), and Far End Block Errors (FEBE). All PM count registers ...

Page 45

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.4.4 Error Monitor The following signal errors are detected in the RCVR: Frame Bit Error (FERR), MFAS Error (MERR), CAS Error (SERR), CRC Error (CERR), and Pulse Density Violations (PDVs). Each error ...

Page 46

Circuit Description 2.4 Receiver 2.4.5 Alarm Monitor The following signal alarms are detected in the RCVR: Loss of Frame (LOF); Loss of Signal (LOS); Analog Loss of Signal (ALOS); Alarm Indication Signal (AIS); Remote Alarm Indication (RAI) or Yellow ...

Page 47

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.4.5.3 Analog Loss of Receive Analog Loss of Signal (RALOS) is declared in analog receive mode, Signal [RDIGI = 0; addr 020], when RTIP/RRING input signal amplitude is less than the programmed ...

Page 48

Circuit Description 2.4 Receiver 2.4.6 Test Pattern Receiver The test pattern receiver circuitry can sync on framed or unframed PRBS patterns and count bit errors. This feature is particularly useful for system diagnostics, production testing, and test equipment applications. ...

Page 49

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.4.7 Receive Framing Two framers are in the receive data stream: an offline framer and an online frame status monitor. The offline framer recovers receive frame alignment; the online framer monitors frame ...

Page 50

Circuit Description 2.4 Receiver The online framer continuously monitors for RLOF condition [ALM1; addr 047] and searches for E1 multiframe alignment after basic frame alignment is recovered by the offline framer. Receive multiframe alignment is declared when multiframe alignment ...

Page 51

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Table 2-3. Criteria for Loss/Recovery of Receive Framer Alignment ( Mode FAS Basic Frame Alignment (BFA) is recovered when the following search criteria are satisfied: FAS pattern (0011011) is found ...

Page 52

Circuit Description 2.4 Receiver Table 2-3. Criteria for Loss/Recovery of Receive Framer Alignment ( Mode SF Superframe alignment is recovered when terminal frame alignment is recovered, identifying Ft bits. Depends on SF submode: if JYEL, only Ft ...

Page 53

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface The offline framer is shared between the RCVR and XMTR and can search in only one direction at any time. Consequently, the processor arbitrates which direction is searched by enabling the reframe ...

Page 54

Circuit Description 2.4 Receiver 2.4.8 External Receive Data Link The External Data Link (DL3) provides signal access to any bit(s) in any time slot of all frames, odd frames, or even frames, including T1 framing bits. Pin access to ...

Page 55

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.4.10.1 Data Link The Bt8370 and Bt8375 provide two internal data link controllers, and the Bt8376 Controllers provides a single controller (DL1). DL1 and DL2 control two serial data channels operating at ...

Page 56

Circuit Description 2.4 Receiver The time slot and bit selection are performed through the DL1 Time Slot Enable register [DL1_TS; addr 0A4] and the DL1 Bit Enable register [DL1_BIT; addr 0A5]. The DL1 Time Slot Enable register selects the ...

Page 57

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Figure 2-13. Polled Receive Data Link Processing Wait N Milliseconds Message status contains number of message bytes (X) in FIFO, where (X) equals 0 during idle channel or errored NOTE(S): message. N8370DSE ...

Page 58

Circuit Description 2.4 Receiver Figure 2-14. Interrupt Driven Receive Data Link Processing Read Message Byte from FIFO and Discard (Purge FIFO) Message status contains number of message bytes (X) in FIFO where (X) equals 0 during idle channel or ...

Page 59

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Using the receive FIFO, an entire block of data can be received with very little microprocessor interrupt overhead. Block transfers from the FIFO can be controlled by the Near Full Threshold in ...

Page 60

Circuit Description 2.5 Receive System Bus 2.5 Receive System Bus The Receive System Bus (RSB) provides a high-speed, serial interface between the RCVR and the system bus. The system bus is compatible with the Mitel ST-Bus, the Siemens PEB ...

Page 61

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface The RSB supports five system bus rates (MHz): 1.536, 1.544, 2.048, 4.096, and 8.192. The T1 rate without a framing bit is 1.536 MHz, consisting of 24 time slots. The T1 rate ...

Page 62

Circuit Description 2.5 Receive System Bus The RSB maps line rate time slots to system bus time slots. The 24- (DS1) or 32- (CEPT) line rate time slots can be mapped to 24, 32, 64, or 128 system bus ...

Page 63

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.5.1 Timebase The RSB timebase synchronizes RFSYNC, RMSYNC, and RINDO with the Receive System Bus Clock (RSBCKI). The RSBCKI can be slaved to 4 clock sources: Receive System Bus Clock Input (RSBCKI), ...

Page 64

Circuit Description 2.5 Receive System Bus 2.5.2 Slip Buffer The 64-byte Receive PCM Slip Buffer [RSLIP; addr 1C0 to 1FF] resynchronizes the Receiver Clock (RXCLK) and data (RNRZ) to the Receive System Bus Clock (RSBCK) and data (RPCMO). RSLIP ...

Page 65

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface In Normal mode, the slip buffer total depth is two 193-bit frames (T1) or two 256-bit frames (E1). Data is written to the slip buffer using RXCLK and read from the slip ...

Page 66

Circuit Description 2.5 Receive System Bus 2.5.4 Signaling Stack The Receive Signaling Stack (RSTACK) allows the processor to quickly extract signaling changes without polling every channel. RSTACK is activated on a per-channel basis by setting the Received Signaling Stack ...

Page 67

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.6 Clock Rate Adapter The full function Clock Rate Adapter is included in all Bt8370 and Bt8375 devices. In the Bt8376, the CLADO output is not implemented. The Clock Rate Adapter (CLAD) ...

Page 68

To Receiver To RJAT RXCLK 0 CLADI 1 (RSCALE Factor) (VSCALE Factor (1) JDIR JCLK JEN (JAT_CR reg) CLADV TJAT TXCLK Clock To Monitor Transmitter CLADI[1:0] (CMUX reg) CEN JFREE CPHASE 1 NCO 0 JPHASE ...

Page 69

To Receiver To RJAT RXCLK 0 CLADI 1 (RSCALE Factor) (VSCALE Factor (1) JDIR JCLK JEN (JAT_CR reg) CLADV TJAT TXCLK Clock To Monitor Transmitter CLADI[1:0] (CMUX reg) CEN JFREE CPHASE 1 NCO 0 JPHASE ...

Page 70

Circuit Description 2.6 Clock Rate Adapter JCLK and CLADO are locked to the selected timing reference. The reference frequency can operate line rates any rate supported by the clock rate adapter. See RSCALE[2:0] ...

Page 71

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Tables 2-8 CLADO and CLADI frequencies. Typically, only 1 selection is needed for a given system configuration. The processor reconfigures the timing reference [CEN; addr 090] as needed to respond to system ...

Page 72

Circuit Description 2.6 Clock Rate Adapter Step 4 Configure RSCALE, VSCALE, VSEL, and XSEL from configuration examples. Again, in some cases, two or more configurations are possible for each frequency option. Many other RSCALE and VSCALE values are also ...

Page 73

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Table 2-9. Common CLADI Reference Frequencies and CLAD Configuration Examples ( Phase CLADI Compare Reference RSCALE Frequency (kHz) (kHz) 3088 2 2 6176 2 1544 2 1544 12352 3 1544 ...

Page 74

Circuit Description 2.7 Transmit System Bus 2.7 Transmit System Bus The Transmit System Bus (TSB) consists of a timebase, slip buffer, signaling buffer, and transmit framer between the XMTR and system bus. The system bus is compatible with the ...

Page 75

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Figure 2-24. Transmit System Bus Waveforms TSBCKI Frame TPCMO E1 TINDO TSIGI Frame TPCMI TINDO X ...

Page 76

Circuit Description 2.7 Transmit System Bus 2.7.1 Timebase The TSB timebase synchronizes TPCMI, TFSYNC, TMSYNC, and TINDO with the Transmit System Bus Clock (TSBCK). The TSBCK can be slaved to five different clock sources: Transmit Clock Input (TCKI), Transmit ...

Page 77

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface In Normal mode, the slip buffer total depth is two 193-bit frames (T1), or two 256-bit frames (E1). Data is written to the slip buffer using TSBCK and read from the slip ...

Page 78

Circuit Description 2.7 Transmit System Bus 2.7.4 Transmit Framing The transmit data stream has two framing functions: offline framer and an online framer. transmit frame alignment (TFSYNC). The online framer monitors the frame alignment found by the offline framer ...

Page 79

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface After the offline framer recovers frame alignment, the online framer monitors TLOF and searches for multiframe alignment; the search uses the criteria defined by the Transmit Frame mode [TFRAME; addr 070]. The ...

Page 80

Circuit Description 2.7 Transmit System Bus For applications that frame in both directions, the processor can manually arbitrate among pending reframe requests by controlling the reframe precedence. An example of manual control follows: The status of the offline framer ...

Page 81

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.8 Transmitter The Digital Transmitter (XMTR) inserts T1/E1 overhead data and encodes single rail NRZ data from the TSB into P and N rail NRZ data, suitable for transmission by the TLIU. ...

Page 82

Circuit Description 2.8 Transmitter 2.8.1 External Transmit Data Link The External Data Link (DL3) allows the system to supply externally any bits in any time slot of all frames, odd frames, or even frames, including T1 framing bits. Pin ...

Page 83

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface DL1 and DL2 are configured identically, except for their offset in the register map. The DL1 address range is 0A4 to 0AE, and the DL2 address range is 0AF to 0B9. From ...

Page 84

Circuit Description 2.8 Transmitter The Transmit Data Link FIFO #1 [TDL1; addr 0AD bytes, and very versatile. It can be used as a single-byte transmit buffer or in any number of bytes maximum of ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface The Transmit Data Link Controller can be programmed according to the CPU bandwidth of your system. For systems with 1 CPU dedicated to 1 Bt8370, the data link status can be polled, ...

Page 86

Circuit Description 2.8 Transmitter Figure 2-31. Interrupt Driven Transmit Data Link Processing Message 0x00 Block 1 0x20 Block 2 0x40 Block 3 0x60 Block 4 Bt8370/8375/8376 uses a hierarchical interrupt structure, with 1 top-level Interrupt Request register [IRR; addr ...

Page 87

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.8.2.2 PRM Generator Performance Report Messages (PRMs) are HDLC messages containing path identification and performance monitoring information. If automatic performance report insertion is selected [AUTO_PRM; addr 0AA], a performance report is generated ...

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Circuit Description 2.8 Transmitter 2.8.4 Overhead Pattern Generator The transmit overhead generation circuitry provides the ability to insert all of the overhead associated with the Primary Rate Channel. The following types of overhead pattern generation are supported: Framing patterns, ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Yellow Alarm, also referred to as RAI (Remote Alarm Indication bit pattern Yellow Alarm Generation inserted into the transmit stream to alert far-end equipment that the local receiver cannot recover ...

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Circuit Description 2.8 Transmitter Automatic generation of Yellow Alarm(YB2) is controlled by AUTO_YEL, RLOF, and RLOF_INTEG. If AUTO_YEL is set, Yellow Alarm is generated during a Receive Loss of Frame alignment (RLOF = 1). Optionally, RLOF integration can be ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface The insertion of E1 Multiframe Yellow Alarm is controlled by INS_MYEL. E1 Multiframe Yellow Alarm is inserted only when INS_MYEL is set. Multiframe Yellow Alarm generation can be initiated manually or automatically. ...

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Circuit Description 2.8 Transmitter Patterns are generated in accordance with ITU–T O.150 (10/92), O.151 (10/92), and O.152 (10/92). Enabling ZLIMIT modifies the inserted pattern by limiting the number of consecutive 0s. For the 2E11-1 or 2E15-1 PRBS patterns, 8 ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Fs and MFAS errors are controlled by the TMERR bit in the TERROR register. TMERR commands a single Fs bit error in T1, or MFAS bit error logically inverting ...

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Circuit Description 2.8 Transmitter The HDB3 line code replaces 4 consecutive 0s by 000V or B00V code, where AMI pulse and bipolar violation (see selects the code that forces the BPV output polarity ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface UMC forces DS0 channels containing eight replaced with the 10011000 code, per Bellcore TA-TSY-000278. NOTE: The TPOSO/TNEGO output pins provide access to the P and N rail unipolar data ...

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Circuit Description 2.9 Transmit Line Interface Unit 2.9 Transmit Line Interface Unit The Transmit Line Interface Unit (TLIU), illustrated in and N rail NRZ data to AMI pulses. The P and N rail NRZ data is generated by the ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface The TLIU can be used independently of the XMTR by applying P and N rail NRZ data to the TPOSI and TNEGI pins. between the P and N rail NRZ data, the ...

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Circuit Description 2.9 Transmit Line Interface Unit 2.9.1 Pulse Shape Normalized and isolated AMI output pulses fit the T1/E1 pulse templates in Figures 2-35 Figures 2-36 corner points. An isolated pulse is defined followed by seven ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Figure 2-37. Standard E1 (G.703) Pulse Template 1.5 1 0 -0.8 -0.6 Figure 2-38. E1 (G.703) Pulse Template Test Circuit Bt8370 NOTE(S): 1. For (nominal) ...

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Circuit Description 2.9 Transmit Line Interface Unit Table 2-15. ANSI T1.102, 1993–DS1 Pulse Template Corner Points, Maximum Curve Time (ns) –400 –253 Time (UI) –0.62 –0.39 Normalized 0.05 0.05 Amplitude Table 2-16. ANSI T1.102, 1993–DS1 Pulse Template Corner Points, ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Table 2-20. G.703, 1988–DS1 Pulse Template Corner Points, Minimum Curve Time (ns) –400 –112 Time (UI) –0.62 –0.17 Normalized –0.10 –0.10 Amplitude Table 2-21. G.703, 1988–Pulse Template Corner Points, Maximum Curve Time ...

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Circuit Description 2.9 Transmit Line Interface Unit The pulse shape block receives P and N rail NRZ data. For each mark, it produces a set of eight 6-bit values which define the pulse shape to be transmitted, as illustrated ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface The VSET resistor not only provides a bias current to RPLL and TPLL but also controls the height of the transmit pulse. The VSET value can be fine tuned according to the ...

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Circuit Description 2.9 Transmit Line Interface Unit 2.9.2 Transmit Phase Lock Loop The Transmit Phase Lock Loop (TPLL) operates at a nominal rate of either 1.544 MHz or 2.048 MHz, selected by T1/E1N [CR0; addr 001]. The pull-in and ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.9.2.2 Output Jitter The maximum output jitter generated on XTIP/XRING dependents on the transmit clock source selected. Refer to CLAD and JAT descriptions. 2.9.3 Line Build Out In the Bt8370 long haul ...

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Circuit Description 2.9 Transmit Line Interface Unit Pulse templates for each of the LBO settings are illustrated in through Figure 2-41 LBO Isolated Pulse Template 3.5 3 2.5 2 1 0.5 Figure 2-42. ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Figure 2-43. 15.0 dB LBO Isolated Pulse Template 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 0.5 Figure 2-44. 22.5 dB LBO Isolated Pulse Template 0.5 0.45 0.4 0.35 ...

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Circuit Description 2.9 Transmit Line Interface Unit 2.9.4 Line Driver The line driver provides current drive to the low-power, bipolar analog signal from the transmit Digital-to-Analog Converter (DAC). The transmit DAC converts the coded pulse shape values to properly ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.9.4.2 Return Loss Return loss is the measure of loss in the return path due to an impedance mismatch. To meet a –18 dB transmitter return loss, independent of the cable type, ...

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Circuit Description 2.9 Transmit Line Interface Unit Figure 2-47. Output Pulse Height versus Transmit Termination Impedance 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0 2.9.4.3 Output Enable The bipolar analog output XTIP/XRING can be ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.10 Microprocessor Interface The Microprocessor Interface (MPU) provides the capability to configure the Bt8370, read status registers and counters, and respond to interrupts (see Figure processors. In the Intel mode, the address ...

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Circuit Description 2.10 Microprocessor Interface 2.10.1 Address/Data Bus In Non-multiplexed Address mode, A[8:0] provides the address for register access; in Multiplexed Address mode, A[8] and AD[7:0] provide the address. In both modes, the data bytes flow over the shared ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.10.4 Device Reset The Bt8370/8375/8376 contains three reset methods: internal power-on reset (POR), hardware reset which uses the RST* pin, and software reset which uses the RESET bit in register CR0 [addr ...

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Circuit Description 2.11 Loopbacks 2.11 Loopbacks Bt8370/8375/8376 provides a complete set of loopbacks for diagnostics, maintenance, and troubleshooting. 2.11.1 Remote Line Loopback The remote line loopback loops the RCVR inputs to the XMTR outputs. The loopback provides BPV transparency ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.11.4 Local Analog Loopback RLIU provides a local analog loopback to internally route bipolar data from XTIP/XRING to RTIP/RRING. In the local analog loopback mode, externally applied data on RTIP/RRING inputs is ...

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Circuit Description 2.12 Joint Test Access Group 2.12 Joint Test Access Group The Bt8370/8375/8376 incorporates printed circuit board testability circuits in compliance with IEEE Std. P1149.1a–1993, IEEE Standard Test Access Port and Boundary–Scan Architecture, commonly known as JTAG (Joint ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 2.12.2 Device Identification Register The JTAG ID register consists of a 4-bit version, a 16-bit part number, and an 11-bit manufacturer number (see Table 2-26. Bt8370/8375/8376 Device Identification JTAG Register (1) Version ...

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Circuit Description 2.12 Joint Test Access Group 2-90 Fully Integrated T1/E1 Framer and Line Interface Conexant Bt8370/8375/8376 N8370DSE ...

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Registers Registers shown with a default setting are reset to the indicated value following power-up, software RESET (CR0; addr 001), or hardware reset (RST* pin). Refer to 3.1 Address Map Table 3-1. Address Map ( Address ...

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Registers 3.1 Address Map Table 3-1. Address Map ( Address Acronym (Hex) 00C IER7 00D IER6 00E IER5 00F IER4 010 IER3 011 IER2 012 IER1 013 IER0 014 LOOP 015 DL3_TS 016 DL3_BIT 017 FSTAT 018 ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Table 3-1. Address Map ( Address Acronym (Hex) 020 LIU_CR 021 RSTAT 022 RLIU_CR 023 LPF 024 VGA_MAX 025 EQ_DAT 026 EQ_PTR 027 DSLICE 028 EQ_OUT 029 VGA 02A PRE_EQ ...

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Registers 3.1 Address Map Table 3-1. Address Map ( Address Acronym (Hex) 050 FERR 051 FERR 052 CERR 053 CERR 054 LCV 055 LCV 056 FEBE 057 FEBE 058 BERR 059 BERR 05B RSA4 05C RSA5 05D ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Table 3-1. Address Map ( Address Acronym (Hex) 070 TCR0 071 TCR1 072 TFRM 073 TERROR 074 TMAN 075 TALM 076 TPATT 077 TLB 078 LBP 07B TSA4 07C TSA5 ...

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Registers 3.1 Address Map Table 3-1. Address Map ( Address Acronym (Hex) 0A4 DL1_TS 0A5 DL1_BIT 0A6 DL1_CTL 0A7 RDL1_FFC 0A8 RDL1 0A9 RDL1_STAT 0AA PRM 0AB TDL1_FEC 0AC TDL1_EOM 0AD TDL1 0AE TDL1_STAT 0AF DL2_TS 0B0 ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Table 3-1. Address Map ( Address Acronym (Hex) 0D0 SBI_CR 0D1 RSB_CR 0D2 RSYNC_BIT 0D3 RSYNC_TS 0D4 TSB_CR 0D5 TSYNC_BIT 0D6 TSYNC_TS 0D7 RSIG_CR 0D8 RSYNC_FRM 0D9 SSTAT 0DA STACK ...

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Registers 3.1 Address Map Table 3-1. Address Map ( Address Acronym (Hex) 100–11F TPCn 120–13F TSIGn 140–15F TSLIP_LOn 160–17F TSLIP_HIn ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 3.2 Global Control and Status Registers Unused bits indicated by a dash ( ) are reserved and should be written to 0. Writing to reserved bits has no — effect. 000—Device Identification ...

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Registers 3.2 Global Control and Status Registers Receiver Framer mode—Establishes the offline framer's search criteria for recovery of frame RFRAME[3:0] alignment (reframe). Also works in conjunction with the RLOFA–RLOFD bits [addr 040] to establish the online framer's criteria for ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 002—Jitter Attenuator Configuration (JAT_CR) The processor writes JAT_CR register at power-up, activating the JAUTO and JCENTER bits to initialize the jitter attenuator elastic store. The processor can maximize jitter tolerance by repeating ...

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Registers 3.2 Global Control and Status Registers Enable JCLK Acceleration—When active, the jitter attenuated output clock (JCLK) phase is JAUTO accelerated (added or subtracted) if the elastic store depth is within 1 Unit Interval (UI) of its limit. JCLK ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 3.3 Interrupt Control Register Unused bits indicated by a dash (—) are reserved and should be written to 0. Writing to reserved bits has no effect. 003—Interrupt Request Register (IRR) An IRR ...

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Registers 3.3 Interrupt Control Register Data Link Controller 2 or BOP Receive—Indicates a transmit or receive interrupt issued by DL2 DL2 or BOP transceiver has received a valid priority codeword and updated RBOP [addr 0A2]. The processor reads ISR1 ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 3.4 Interrupt Status Registers Unused bits indicated by a dash (—) are reserved and should be written to 0. Writing to reserved bits has no effect. An Interrupt Status register (ISR) bit ...

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Registers 3.4 Interrupt Status Registers 004—Alarm 1 Interrupt Status (ISR7) All events reported in ISR7 are from dual-edge sources, except Receive Pulse Density Violation [RPDV]. Any transition of real-time status in Alarm 1 Status register [ALM1; addr 047] forces ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 005—Alarm 2 Interrupt Status (ISR6) All events reported in ISR6 are from dual-edge sources, except the 1-second timer [ONESEC] and Transmit Pulse Density Violation [TPDV]. Any transition of real-time status in the ...

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Registers 3.4 Interrupt Status Registers 006—Error Interrupt Status (ISR5) All events in ISR5 are from rising edge sources. Each event is latched active-high and held according to the LATCH_ERR bit [addr 046] and triggers an interrupt if the corresponding ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 007—Counter Overflow Interrupt Status (ISR4) All count overflow events in ISR4 are caused by rising edge sources. Each event is latched active-high when the respective error counter [addr 050–05A] reaches its maximum ...

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Registers 3.4 Interrupt Status Registers Receive Signaling Stack—Indicates 1 or more signaling bit changes were detected during the RSIG prior receive multiframe, and new ABCD (robbed bit or CAS) signaling is available on the Receive Signaling Stack register [addr ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 00A—Data Link 2 Interrupt Status (ISR1) All events in ISR1 are from rising edge sources. Each event is latched active-high and held until the processor read clears ISR1. Each event triggers an ...

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Registers 3.4 Interrupt Status Registers 00B—Pattern Interrupt Status (ISR0) All events in ISR0 are caused by rising edge sources. Each event is latched active-high and held until the processor read clears ISR0. Each event triggers an interrupt if the ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 3.5 Interrupt Enable Registers Unused bits indicated by a dash ( ) are reserved and should be written to 0. Writing to reserved bits has no — effect. Writing ...

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Registers 3.5 Interrupt Enable Registers 00E—Error Interrupt Enable Register (IER5 TSLIP RSLIP CKERR Enable TSLIP Interrupt TSLIP Enable RSLIP Interrupt RSLIP Enable CKERR Interrupt CKERR Enable JERR Interrupt JERR Enable CERR Interrupt CERR Enable SERR Interrupt ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 010—Timer Interrupt Enable Register (IER3 TSIG TMSYNC TMF Enable TSIG Interrupt TSIG Enable TMSYNC Interrupt TMSYNC Enable TMF Interrupt TMF Enable TFRAME Interrupt TFRAME Enable RSIG Interrupt RSIG Enable ...

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Registers 3.5 Interrupt Enable Registers 012—Data Link 2 Interrupt Enable Register (IER1 RBOP RFULL2 RNEAR2 RBOP — — Enable RBOP Interrupt RBOP Enable RFULL Interrupt RFULL2 Enable RNEAR Interrupt RNEAR2 Enable RMSG Interrupt ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 3.6 Primary Control and Status Registers Unused bits indicated by a dash ( ) are reserved and should be written to 0. Writing to reserved bits has no — effect. 014—Loopback Configuration ...

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Registers 3.6 Primary Control and Status Registers Enable Local Analog Loopback—Bipolar data from XTIP/XRING is internally connected to ALOOP RTIP/RRING inputs. Externally applied data on RTIP/RRING inputs is ignored. XTIP/XRING output data is unaffected. After ALOOP activation or deactivation, ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface External Data LinkTime Slot Select—Picks 1 8-bit time slot for input and output over the TS[4:0] external data link pins. Any time slot can be chosen from TS0 to TS31 in E1 ...

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Registers 3.6 Primary Control and Status Registers Frame Search Successful—Active-high indicates the offline framer located the frame FOUND alignment according to the selected receive or transmit framer mode. Refer to maximum average reframe time. Upon detection of frame alignment, ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Framer Search Timeout—Cleared when the offline framer transitions to its ACTIVE state. If TIMEOUT multiple frame candidates exist over the entire mode-dependent timeout interval (refer to Table 3-5), TIMEOUT is latched active-high. ...

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Registers 3.6 Primary Control and Status Registers 018—Programmable Input/Output (PIO ONESEC_IO RDL_IO TDL_IO Bidirectional ONESEC Input/Output mode—Selects input or output mode for ONESEC signal ONESEC_IO pin, and controls the internal timer interval used for 1-second status ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Bidirectional RFSYNC Input/Output mode—Refer to system bus sync mode summary in RFSYNC_IO Tables 3-6 and 3-8. When RFSYNC is an input, its low-to-high transition aligns the RSB timebase to the programmed RSB.OFFSET. ...

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Registers 3.6 Primary Control and Status Registers Table 3-7. Common TFSYNC and TMSYNC Configurations Conditions TFSYNC Transmit framer disabled. IN (TABORT = 1) IN-GND IN IN OUT OUT Transmit framer enabled to OUT search TPCMI for embedded framing. (EMBED ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 019—Programmable Output Enable (POE — — TDL_OE TDLCKO Output Buffer Control—When enabled, TDLCKO is output according to DL3_TS TDL_OE and DL3_BIT [addr 015, 016]. Note that TDL_IO [addr 018] ...

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Registers 3.6 Primary Control and Status Registers 01A—Clock Input Mux (CMUX RSBCKI[1] RSBCKI[0] TSBCKI[1] RSBCKI Source Select—The internal clock mux selects 1 of four clock signals for application RSBCKI[1:0] to the RSB timebase. RSBCKI input pin ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface TCKI Source Select—The internal transmit clock mux selects 1 of four clock signals. The TCKI[1:0] selected clock signal is applied to the transmit clock monitor and is a timing reference for the ...

Page 156

Receive LIU Registers 3 3.7 Receive LIU Registers Unused bits indicated by a dash ( ) are reserved and should be written to 0. Writing to reserved bits has no — effect. Table 3-9 details receiver LIU register settings ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 020—LIU Configuration (LIU_CR) Bits 0 and 1 are reserved and should be written to the values shown. NOTE RST_LIU SQUELCH FORCE_VGA Reset RLIU—Writing RST_LIU resets the ...

Page 158

Receive LIU Registers 021—Receive LIU Status (RSTAT JMPTY CPDERR ZCSUB CLAD Phase Detector Error—Indicates the CLAD phase detector has lost lock with respect to CPDERR the selected CLADI reference clock. JAT Empty/Full—Indicates whether the elastic store ...

Page 159

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Bipolar Violation—Reports one or more bipolar violations detected on RTIP/RRING data BPV inputs. Depending on RZCS [addr 040], the BPV may include bipolar violations received as part of a B8ZS or HDB3 ...

Page 160

Receive LIU Registers Disable Automatic RLBO—When active, automatic RLBO switching is disabled when the OOR_BLOCK ADC is out of range. Receiver Line Build Out—Enables receive signal attenuation. RLB0 Eye Open Timeout LONG_EYE 023—RPLL Low Pass Filter (LPF ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 025—Equalizer Coefficient Data Register (EQ_DAT EQ_DAT[7] EQ_DAT[6] EQ_DAT[5] Default value is set internally during RESET or RST_LIU. EQ_DAT[7:0] 026—Equalizer Coefficient Table Pointer (EQ_PTR — — EQ_PTR[5] ...

Page 162

Receive LIU Registers 028—Equalizer Output Levels EQ_OUT[7] EQ_OUT[6] EQ_OUT[5] All EQ_OUT register bits are internally set to a default value during RESET. Under normal EQ_OUT7:0] line operating conditions, the processor should not change this default value. ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Figure 3-1. Receive Equalizer Eye Pattern Output 029—Variable Gain Amplifier Status — — VGA[5] Indicates the current VGA gain level. The processor must write to this register (any value) ...

Page 164

Receive LIU Registers 02A—Pre_Equalizer (PRE_EQ FORCE ON Internally set to default value during RESET or RST_LIU. PRE_EQ is an analog filter that PRE_EQ[7:0] resides after the VGA and which operates independently of the adaptive digital equalizer. ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 3.8 Receiver Registers Unused bits indicated by a dash ( ) are reserved and should be written to 0. Writing to reserved bits has no — effect. 040—Receiver Configuration (RCR0 ...

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Receiver Registers RX Reframe Criteria—Determines the number of frame errors the online framer must detect RLOFD–RLOFA before declaring a loss of frame alignment [ALM1; addr 047]. Refer to the Receive Framer mode in [RFRAME; addr 001] Alignment) to find ...

Page 167

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface PRBS Framed—When set, PRBS test pattern bits are not checked during framing bit positions. FRAMED In T1 mode, F-bit locations are not searched mode, time slot 0 and time slot ...

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Receiver Registers 042—Receive Loopback Code Detector Configuration (RLB — — — Loopback Deactivate Code Length—Selects the number of loopback pattern bits from LBD DN_LEN[1:0] [addr 044] that are compared to received data to determine it a ...

Page 169

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 044—Loopback Deactivate Code Pattern (LBD LBD[1] LBD[2] LBD[3] First bit expected of LOOPDN pattern LBD[1] Second bit expected of LOOPDN pattern LBD[2] Third bit expected of LOOPDN pattern LBD[3] ...

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Receiver Registers Enable RLOF Integration—When set, the receive loss of frame status [RLOF; addr 047] is RLOF_INTEG integrated for 2.0 to 2.5 seconds during T1 framer modes (not applicable to E1 modes). RLOF interrupt status [ISR7; addr 004] is ...

Page 171

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Enable ONESEC Latching of Errors—Determines the interval for which latched active errors LATCH_ERR are held in error interrupt [ISR5; addr 006] and in pattern interrupt [ISR0; addr 00B] status. IER 0 0 ...

Page 172

Receiver Registers Table 3-13. Receive Yellow Alarm Set/Clear Criteria Mode Y0 Set for 4 frames (500 consecutive NFAS frames each contain TS0 bit Cleared for 4 frames if 2 consecutive NFAS frames each ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Receive Yellow Alarm—Real-time or integrated RYEL status depends on both the selected RYEL receive framer and Yellow Alarm integration modes [YEL_INTEG; addr 045]. Refer to Table 3-12, Receive Yellow Alarm Set/Clear Criteria ...

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Receiver Registers Receive Loss of Frame Alignment—Real-time or integrated RLOF status depends on selected RLOF receive framer mode, out of frame criteria [RLOFA–RLOFD; addr 040], and integration mode [RLOF_INTEG; addr 045]. Refer to frame bits are monitored. Refer to ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 049—Alarm 3 Status (ALM3) Reports real-time status of the receive framer (not affected by ONESEC latch mode), and miscellaneous latched error status (SEF and RMAIS). Any change of the logical OR of ...

Page 176

Performance Monitoring Registers 3.9 Performance Monitoring Registers Unused bits indicated by a dash ( ) are reserved and should be written to 0. Writing to reserved bits has no — effect. If the counter overflow interrupt [IER4; addr 00F] ...

Page 177

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 053—CRC Error Counter MSB (CERR) If LATCH_CNT [addr 046] is inactive, reading CERR [addr 053] clears the entire CERR[9:0] count value CRC6/CRC4 Error Count CERR[9:8] 054—Line ...

Page 178

Performance Monitoring Registers 058—PRBS Bit Error Counter LSB (BERR) Reading BERR transfers the most recent 12-bit count from the internal PRBS error counter to BERR[11:0], and clears the internal error counter without affecting the reported BERR[11:0] value. Subsequent reads ...

Page 179

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 3.10 Receive Sa-Byte Buffers Unused bits indicated by a dash (—) are reserved and should be written to 0. Writing to reserved bits has no effect. Five receive Sa-Byte buffers [RSA4–RSA8] are ...

Page 180

Receive Sa-Byte Buffers 05D—Receive Sa6 Byte Buffer (RSA6 RSA6[7] RSA6[6] RSA6[5] Sa6 bit received in frame 15 RSA6[7] Sa6 bit received in frame 13 RSA6[6] Sa6 bit received in frame 11 RSA6[5] Sa6 bit received in ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 05F—Receive Sa8 Byte Buffer (RSA8 RSA8[7] RSA8[6] RSA8[5] Sa8 bit received in frame 15 RSA8[7] Sa8 bit received in frame 13 RSA8[6] Sa8 bit received in frame 11 RSA8[5] ...

Page 182

Transmit LIU Registers 3.11 Transmit LIU Registers Unused bits indicated by a dash ( ) are reserved and should be written to 0. Writing to reserved bits has no — effect. 060–067—Transmit Pulse Shape Configuration (SHAPE ...

Page 183

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Table 3-14. Return Loss Values TURNS TERM R TERM 0 0 None None 0 0 None ...

Page 184

Transmit LIU Registers Select Transmit Pulse Template—Each positive or negative pulse output on XTIP/XRING is PULSE[2:0] shaped to meet the transmit pulse template according to the selected cable length and type. (Refer to Figure 2-34, TLIU Waveform T1/E1 isolated ...

Page 185

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 3 3.12 Transmitter Registers Unused bits indicated by a dash ( ) are reserved and should be written to 0. Writing to reserved bits has no — effect. 070—Transmit Framer Configuration (TCR0) ...

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Transmitter Registers Table 3-15. E1 Transmit Framer Modes (T1/E1N = 0) TFRAME Framer Mode 00XX FAS Only 01XX FAS + MFAS 10XX FAS + CAS 11XX FAS + MFAS + CAS Table 3-16. T1 Transmit Framer Modes (T1/E1N = ...

Page 187

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Table 3-17. Criteria for E1 Loss/Recovery of Transmit Frame Alignment Mode FAS Basic Frame Alignment (BFA) is recovered when the following search criteria are satisfied: FAS pattern (0011011) is found in frame ...

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Transmitter Registers Table 3-18. Criteria for T1 Loss/Recovery of Transmit Frame Alignment Mode FT Only Terminal Frame Alignment is recovered when One, and only 1 valid Ft pattern (1010) is found in 12 alternate F-bit locations (3 ms), when ...

Page 189

Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 071—Transmitter Configuration (TCR1 TNRZ TABORT TFORCE Transmit NRZ Data—Transmit dual-rail unipolar outputs TPOSO/TNEGO are replaced by TNRZ non-return to 0 unipolar data (TNRZO) and transmit multiframe sync (MSYNCO). Both ...

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Transmitter Registers Transmit Loss of Frame Criteria—Determines the number of frame errors that the online TLOFC–TLOFA framer must detect before declaring a loss of frame alignment [TLOF; addr 048]. Refer to TFRAME [addr 070] to find which frame bits ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 072—Transmit Frame Format (TFRM) TFRM controls the insertion of overhead bits generated by transmit frame and alarm formatters. Bypassed overhead bits flow transparently from TPCMI system bus input through TSLIP buffer. 7 ...

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Transmitter Registers 073—Transmit Error Insert (TERROR) Transmit error insertion capabilities are provided for system diagnostic, production test, and test equipment applications. Writing any TERROR bit injects a single occurrence of the respective error on TPOSO/TNEGO and ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Inject Line Code Violation—Injects a single LCV error depending on the line mode and the TVERR selected ZCS mode, the LCV injector waits for transmission of two consecutive pulses on ...

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Transmitter Registers 075—Transmit Alarm Signal Configuration (TALM — — AUTO_MYEL Automatic Manual Transmit Multiframe Yellow Alarm—Applicable to E1 modes only. AUTO_MYEL /TMYEL Automatic mode sends Multiframe Yellow Alarm for the duration of a receive loss of ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface Automatic Manual Transmit Alarm Indication Signal—When activated manually (TAIS) or AUTO_AIS /TAIS automatically (AUTO_AIS), the alarm formatter replaces all data output on TPOSO/TNEGO and XTIP/XRING with an unframed all-1s signal (AIS). This ...

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Transmitter Registers PRBS test patterns used by RPATT [addr 041] and TPATT [addr 076] are defined in the ITU TPATT[1:0] standards O.151 and O.152 to use either inverted or non-inverted data. Bt8370/8375/8376 uses standard data inversion for the selected ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 077—Transmit Inband Loopback Code Configuration (TLB — — — Inband Loopback Code Length (from LBP): LB_LEN[1:0] Loopback Code Overwrites Framing UNFRAMED Start Inband Loopback Code Transmission LBSTART 078—Transmit Inband ...

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Transmit Sa-Byte Buffers 3.13 Transmit Sa-Byte Buffers Unused bits indicated by a dash ( ) are reserved and should be written to 0. Writing to reserved bits has no — effect. Five transmit Sa-Byte buffers (TSA4–TSA8) are used to ...

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Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 07D—Transmit Sa6 Byte Buffer (TSA6 TSA6[7] TSA6[6] TSA6[5] Sa6 bit transmitted in frame 15 TSA6[7] Sa6 bit transmitted in frame 13 TSA6[6] Sa6 bit transmitted in frame 11 TSA6[5] ...

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Transmit Sa-Byte Buffers 07F—Transmit Sa8 Byte Buffer (TSA8 TSA8[7] TSA8[6] TSA8[5] Sa8 bit transmitted in frame 15 TSA8[7] Sa8 bit transmitted in frame 13 TSA8[6] Sa8 bit transmitted in frame 11 TSA8[5] Sa8 bit transmitted in ...

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