AD9577BCPZ-R7 Analog Devices Inc, AD9577BCPZ-R7 Datasheet - Page 39

• Manufacturer Part Number: AD9577BCPZ-R7
• Manufacturer: Analog Devices Inc

Specifications of AD9577BCPZ-R7

• Lead Free Status / Rohs Status: Compliant

Data Sheet
Table 30. Internal Register Map
Register
Name
C0
X0
BP0
AF0
BF3
BF0
BF1
BF2
ABF0
ADV0
ADV1
ADV2
BDV0
BDV1
BDV2
BS1
BS2
BS3
AM0
AM1
AM2
BM0
BM1
BM2
BM3
BM4
BM5
DR1
DR2
G0
R/W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
0x1C
0x19
0x1B
0x25
0x26
0x2A
0x2B
0x2C
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x3A
0x3B
0x3D
Addr
0x40
0x1F
0x11
0x18
0x1A
0x1D
0x22
0x23
0x24
0x27
D7
0
0
0
0
0
1
0
0
NumSteps[0]
0
0
PDCH3
0
0
V0[2:0], Channel 0 VCO divider;
V1[2:0], Channel 1 VCO divider;
FRAC[3:0], SDM fractional word; MARGIN = 1
V3[2:0], Channel 3 VCO divider;
V2[2:0], Channel 2 VCO divider;
V0[2:0], Channel 0 VCO divider
V1[2:0], Channel 1 VCO divider
V2[2:0], Channel 2 VCO divider
V3[2:0], Channel 3 VCO divider
FRAC[3:0], SDM fractional word
MARGIN = 1
MARGIN = 1
MARGIN = 1
MARGIN = 1
NumSteps[8:1], number of fractional word increments/decrements per half triangular-wave cycle
D6
0
0
0
0
0
1
0
0
0
0
PDCH2
0
0
CkDiv[6:0], reference divider output is divided by this integer to determine SSCG update rate
0
D5
0
0
0
0
0
0
0
FORMAT2[2:0], output format selection
Rev. 0 | Page 39 of 44
FRAC[11:4], SDM fractional word; MARGIN = 1
D4
0
0
0
PD_SDM
0
0
0
0
for PLL2 (see
FracStep[7:0], SSCG fractional step size
MOD[7:0], SDM modulus; MARGIN = 1
FRAC[11:4], SDM fractional word
MOD[7:0], SDM modulus
Na[5:0], PLL1 feedback divider ratio divider; MARGIN = 1
Nb[5:0], PLL2 feedback divider ratio divider; MARGIN = 1
D3
0
0
0
0
0
0
0
PDPLL1, power-
down PLL1
Table 21
D0[4:0], Channel 0 output divider value; MARGIN = 1
D1[4:0], Channel 1 output divider value; MARGIN = 1
D3[4:0], Channel 3 output divider value; MARGIN = 1
D2[4:0], Channel 2 output divider value; MARGIN = 1
Nb[5:0], PLL2 feedback divider ratio
Na[5:0], PLL1 feedback divider ratio
D0[4:0], Channel 0 output divider value
D1[4:0], Channel 1 output divider value
D2[4:0], Channel 2 output divider value
D3[4:0], Channel 3 output divider value
)
MOD[11:8], SDM modulus; MARGIN = 1
MOD[11:8], SDM modulus
D2
0
0
Bleed
0
0
0
0
PDPLL2, power-
down PLL2
FORMAT1[2:0], output format selection for
PLL1 (see
D1
EnI2C
0
PDCH1
0
0
0
0
R; 0 =
divide by 1
Table 20
)
AD9577
D0
0
NewAcq
PDCH0
0
SyncCh01
SyncCh23
PDRefOut
0