AD9577BCPZ-R7 Analog Devices Inc, AD9577BCPZ-R7 Datasheet - Page 14

• Manufacturer Part Number: AD9577BCPZ-R7
• Manufacturer: Analog Devices Inc

Specifications of AD9577BCPZ-R7

• Lead Free Status / Rohs Status: Compliant

AD9577
POWER
Table 9.
Parameter
POWER SUPPLY
LVPECL POWER DISSIPATION
LVDS POWER DISSIPATION
CMOS POWER DISSIPATION
POWER CHANGES
Power-Down 1 LVPECL Channel
Power-Down 1 LVDS Channel
Power-Down 1 CMOS Channel
Min
3.0
160
105
130
Typ
3.3
1235
1270
1020
1085
1065
1190
205
155
170
Max
3.6
1490
1530
1200
1290
1380
1510
Unit
V
mW
mW
mW
mW
mW
mW
mW
mW
mW
Rev. 0 | Page 14 of 44
Test Conditions/Comments
Typical part configuration, both PLLs enabled for integer-N operation,
f
Na = 100, V0 = 4, D0 = 4, V1 = 4, D1 = 5, Nb = 96, V2 = 4, D2 = 6, V3 = 4,
D3 = 18, 25 MHz crystal used, load is 200 Ω to GND at output pins, then
ac-coupled to 50 Ω terminated measurement equipment
Worst-case part configuration, PLL2 in fractional-N mode, with SSCG
enabled, f
f
V2 = 3, D2 = 2, V3 = 3, D3 = 2, FRAC = 300, MOD = 1250, CkDiv = 5,
NumSteps = 77, FracStep = −7, −0.5% downspread at 32 kHz,
25 MHz crystal used, load is 200 Ω to GND at output pins, then
ac-coupled to 50 Ω terminated measurement equipment
Typical part configuration, both PLLs enabled for integer-N operation,
f
Na = 100, V0 = 4, D0 = 4, V1 = 4, D1 = 5, Nb = 96, V2 = 4, D2 = 6, V3 = 4,
D3 = 18, 25 MHz crystal used, load ac-coupled to measurement
equipment that provides 100 Ω differential input termination
Worst-case part configuration, PLL2 in fractional-N mode, with SSCG
enabled, f
f
V2 = 3, D2 = 2, V3 = 3, D3 = 2, FRAC = 300, MOD = 1250, CkDiv = 5,
NumSteps = 77, FracStep = −7, −0.5% downspread at 32 kHz,
25 MHz crystal used, load ac-coupled to measurement equipment
that provides 100 Ω differential input termination
Typical part configuration, both PLLs enabled for integer-N operation,
f
Na = 100, V0 = 4, D0 = 4, V1 = 4, D1 = 5, Nb = 96, V2 = 4, D2 = 6, V3 = 4,
D3 = 18, 25 MHz crystal used, eight single-ended outputs active,
C
Worst-case part configuration, PLL2 in fractional-N mode, with SSCG
enabled, f
f
V2 = 3, D2 = 4, V3 = 3, D3 = 4, FRAC = 300, MOD = 1250, CkDiv = 5,
NumSteps = 77, FracStep = −7, −0.5% downspread at 32 kHz,
25 MHz crystal used, eight single-ended outputs active, C
Reduction in power due to turning off a channel of one VCO divider,
one output divider, and one output buffer; data for Channel 1, with
typical part configuration, both PLLs enabled for integer-N operation,
f
Na = 100, V0 = 4, D0 = 4, V1 = 4, D1 = 5, Nb = 96, V2 = 4, D2 = 6, V3 = 4,
D3 = 18, 25 MHz crystal used
Load 200 Ω to GND at output pins, and ac-coupled to 50 Ω terminated
measurement equipment
Load ac-coupled to measurement equipment that provides 100 Ω
differential input termination
Eight single-ended outputs active, C
OUT0
OUT3
OUT0
OUT3
OUT0
OUT3
OUT0
LOAD
= 156.25 MHz, f
= 359.33 MHz, Na = 91, V0 = 3, D0 = 2, V1 = 3, D1 = 2, Nb = 86,
= 156.25 MHz, f
= 359.33 MHz, Na = 91, V0 = 3, D0 = 2, V1 = 3, D1 = 2, Nb = 86,
= 156.25 MHz, f
= 179.66 MHz, Na = 91, V0 = 3, D0 = 4, V1 = 3, D1 = 4, Nb = 86,
= 156.25 MHz, f
= 5 pF
OUT0
OUT0
OUT0
= 379.16 MHz, f
= 379.16 MHz, f
= 189.58 MHz, f
OUT1
OUT1
OUT1
OUT1
= 125 MHz, f
= 125 MHz, f
= 125 MHz, f
= 125 MHz, f
OUT1
OUT1
OUT1
= 379.16 MHz, f
= 379.16 MHz, f
= 189.58 MHz, f
OUT2
OUT2
OUT2
OUT2
LOAD
= 100 MHz, f
= 100 MHz, f
= 100 MHz, f
= 100 MHz, f
= 5 pF
OUT2
OUT2
OUT2
= 359.33 MHz,
= 359.33 MHz,
= 179.66 MHz,
OUT3
OUT3
OUT3
OUT3
= 33.33 MHz,
= 33.33 MHz,
= 33.33 MHz,
= 33.33 MHz,
Data Sheet
LOAD
= 5 pF