AD9577BCPZ-R7 Analog Devices Inc, AD9577BCPZ-R7 Datasheet - Page 37

• Manufacturer Part Number: AD9577BCPZ-R7
• Manufacturer: Analog Devices Inc

Specifications of AD9577BCPZ-R7

• Lead Free Status / Rohs Status: Compliant

Data Sheet
MAX_BW
The normal bandwidth of PLL2 is 50 kHz. This low bandwidth
is required to filter the SDM phase noise. When SSCG is activated,
the bandwidth is increased to 125 kHz. There is a trade-off in
setting the PLL bandwidth between allowing the triangular-wave
modulation (that is, its higher order harmonics) to pass through
the PLL unattenuated and passing more SDM phase noise through
to the PLL output. Bringing the MAX_BW pin high changes the
Table 29. Register Values for SSCG Example
Parameter
NumSteps
FracStep
CkDiv
FRAC
MOD
Nb
Register Name
BS2[7:0], BS3[7]
BS1[7:0]
BS3[6:0]
BF0[7:0], BF1[7:4]
BF1[3:0], BF2[7:0]
BF3[5:0]
Range
+1 to +511
−128 to 0
+2 to +127
0 to +4094
0 to +4095
0 to +63
Rev. 0 | Page 37 of 44
PLL bandwidth to 250 kHz from its default value of 125 kHz
during SSCG operation. Increasing the PLL bandwidth results
in more SDM phase noise being passed unfiltered through to the
PLL output, but more of the triangular-wave harmonics are also
passed through, improving the triangular-wave accuracy.
Value (Decimal)
+45
−7
+9
+198
+625
80 + 20 = 100
Value(Binary)
00101101
11111001
0001001
000011000110
001001110001
010100
AD9577