AD9577BCPZ-R7 Analog Devices Inc, AD9577BCPZ-R7 Datasheet - Page 38

• Manufacturer Part Number: AD9577BCPZ-R7
• Manufacturer: Analog Devices Inc

Specifications of AD9577BCPZ-R7

• Lead Free Status / Rohs Status: Compliant

AD9577
I
2
C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
SDA
SCL
START BIT
S
S = START BIT
A(S) = ACKNOWLEDGE BY SLAVE
S
A6
SLAVE ADDR, LSB = 0 (WR)
SLAVE ADDRESS
SDA
SCL
A5
S
t
F
SLADDR[4:0]
S
SLAVE ADDR, LSB = 0 (WR) A(S)
t
t
LOW
HD;STA
A(S)
t
HD;DAT
SUB ADDR
t
R
WR
t
1
SU;DAT
Figure 44. Slave Address Configuration
SLAVE ADDRESS [6:0]
P = STOP BIT
A(M) = ACKNOWLEDGE BY MASTER
Figure 47. I
Figure 48. I
Figure 45. I
Figure 46. I
0
ACK
A(S)
0
Rev. 0 | Page 38 of 44
t
SUB ADDR
SUB ADDRESS
S
HIGH
t
F
2
2
2
C Data Transfer Timing
C Port Timing Diagram
2
A7
0
SLAVE ADDR, LSB = 1 (RD)
C Write Data Transfer
C Read Data Transfer
SUB ADDR[6:1]
t
SU;STA
0
A(S)
0
DATA
0
0 = WR
1 = RD
S
CTRL
R/W
A0
A(S)
X
A(M) = LACK OF ACKNOWLEDGE BY MASTER
t
SU;STO
A(S) DATA A(M)
t
HD;STA
ACK
DATA
D7
DATA
P
A(S)
DATA[6:1]
t
BUF
t
P
R
DATA
S
A(M)
D0
P
ACK
Data Sheet
STOP BIT
P