MAX9850ETI+ Maxim Integrated Products, MAX9850ETI+ Datasheet - Page 29

• Manufacturer Part Number: MAX9850ETI+
• Description: IC AMP AUDIO .095W STER 28TQFN
• Manufacturer: Maxim Integrated Products
• Series: DirectDrive™r
• Type: Class ABr

Specifications of MAX9850ETI+

• Output Type: Headphones, 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 95mW x 2 @ 16 Ohm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Features: DAC, Depop, Digital Inputs, I²C, I²S, Line Level Inputs & Outputs, Mute, Shutdown, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 28-WQFN Exposed Pad, 28-HWQFN
• Product: General Purpose Audio Amplifiers
• Output Power: 95 mW
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 7.6 mA
• Maximum Power Dissipation: 2857 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.8 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A master reading data from the MAX9850 transmits the
proper slave address followed by a series of nine SCL
pulses. The MAX9850 transmits data on SDA in sync with
the master-generated SCL pulses. The master acknowl-
edges receipt of each byte of data. Each read sequence
is framed by a START or REPEATED START condition, a
not acknowledge, and a STOP condition.
SDA operates as both an input and an open-drain out-
put. A pullup resistor, typically greater than 500Ω, is
required on the SDA bus. SCL operates as an input only.
A pullup resistor, typically greater than 500Ω, is required
on SCL if there are multiple masters on the bus, or if the
Figure 4. Right-Justified, and Left-Justified Audio Data Formats (Slave Mode, 16-Bit Data)
Figure 5. 2-Wire Interface Timing Diagram
SDA
SCL
LRCLK
LRCLK
LRCLK
BCLK
BCLK
BCLK
SDIN
SDIN
SDIN
t
HD, STA
LEFT-JUSTIFIED
DIGITAL AUDIO REGISTER (0xA)
CONTENTS = 00000000
RIGHT-JUSTIFIED
DIGITAL AUDIO REGISTER (0xA)
CONTENTS = 00000100
I
DIGITAL AUDIO REGISTER (0xA)
CONTENTS = 00001000
2
S
CONDITION
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
START
X
15
______________________________________________________________________________________
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
t
LOW
t
R
t
t
SU, DAT
Stereo Audio DAC with DirectDrive
HIGH
LEFT
LEFT
LEFT
t
F
t
HD, DAT
t
HD, STA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X
master in a single-master system has an open-drain SCL
output. Series resistors in line with SDA and SCL are
optional. Series resistors protect the digital inputs of the
MAX9850 from high-voltage spikes on the bus lines, and
minimize crosstalk and undershoot of the bus signals.
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the
I
2
CONDITION
15
REPEATED
C bus is not busy.
START
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Headphone Amplifier
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
t
HD, STA
RIGHT
RIGHT
RIGHT
t
SP
t
SU, STO
CONDITION
STOP
t
BUF
CONDITION
Bit Transfer
START
29