MAX9850ETI+ Maxim Integrated Products, MAX9850ETI+ Datasheet - Page 26

• Manufacturer Part Number: MAX9850ETI+
• Description: IC AMP AUDIO .095W STER 28TQFN
• Manufacturer: Maxim Integrated Products
• Series: DirectDrive™r
• Type: Class ABr

Specifications of MAX9850ETI+

• Output Type: Headphones, 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 95mW x 2 @ 16 Ohm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Features: DAC, Depop, Digital Inputs, I²C, I²S, Line Level Inputs & Outputs, Mute, Shutdown, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 28-WQFN Exposed Pad, 28-HWQFN
• Product: General Purpose Audio Amplifiers
• Output Power: 95 mW
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 7.6 mA
• Maximum Power Dissipation: 2857 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.8 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1 = ALERT sets to 1 when either IOHL or IOHR set to 1.
0 = ALERT will not set when IOHL or IOHR set to 1.
IIOH = 1 configures the MAX9850 to set ALERT = 1
when one or both of the headphone amplifier outputs
(HPL, HPR) has experienced an overcurrent condition.
Program GM(1:0), while GPD = 1, to configure GPIO as
a hardware interrupt to alert a µC to an overcurrent con-
dition on the headphone outputs.
1 = The MAX9850 is powered on.
0 = The MAX9850 is in low-power shutdown mode. The
I
Set SHDN = 1 to power on the MAX9850. The head-
phone amplifier, master clock, line inputs/outputs, DAC,
charge pump, and charge-pump clock all have their
own enable bits. The individual components of the
MAX9850 can only be enabled after SHDN = 1.
1 = MCLK is connected to the MAX9850.
0 = MCLK is disconnected from the MAX9850.
MCLKEN must be set to 1 for the DAC to operate prop-
erly. The line inputs/outputs and headphone amplifiers
will work if MCLKEN = 0, but the charge-pump clock
must be derived from the internal oscillator.
11 = Enable the internal charge pump.
00 = Disable the internal charge pump.
10 and 01 = Invalid.
Set CPEN(1:0) to 11 to enable the internal charge
pump when the line outputs and headphone amplifiers
are used.
1 = Enable the headphone outputs.
0 = Disable the headphone outputs.
Set HPEN = 1 to enable the headphone outputs. HPEN
= 0 places the headphone outputs in high impedance.
The line outputs must be enabled for the headphone
amplifiers to operate properly.
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Table 16. Enable (0x5) Read/Write, Bit
Descriptions
26
2
SHDN MCLKEN CPEN (1:0)
C interface remains active.
B7
______________________________________________________________________________________
Headphone Overcurrent Interrupt Enable (IIOH)
B6
B5
Headphone Output Enable (HPEN)
Charge-Pump Enable (CPEN(1:0))
B4
HPEN LNOEN LNIEN DACEN
MCLK Enable (MCLKEN)
B3
Enable Register
Shutdown (
B2
B1
SHDN )
B0
1 = Enable the line outputs.
0 = Disable the line outputs.
LNOEN = 0 forces the line outputs and the headphone
outputs to high impedance. Set LNOEN = 1 to enable
the line outputs. The line outputs must be enabled for
the headphone amplifiers to operate properly.
1 = Enable the line inputs.
0 = Disable the line inputs.
LNIEN = 1 enables the line inputs. LNIEN = 0 discon-
nects the line inputs.
1 = Enable the audio DAC.
0 = Disable the audio DAC.
DACEN = 1 enables the DAC and all supporting circuit-
ry including the digital audio interface and interpolating
FIR filter. DACEN = 0 places the DAC and support cir-
cuitry into low-power shutdown mode.
00 = Internal clock divider is transparent (f
f
01 = (f
10 = (f
11 = (f
IC(1:0) controls the internal clock divider that determines
the internal clock frequency from the master clock.
Table 17. Clock (0x6) Read/Write, Bit
Descriptions
Table 18. Charge Pump (0x7) Read/Write,
Bit Descriptions
MCLK
B7
B7
0
SR(1:0)
).
ICLK
ICLK
ICLK
B6
B6
0
= f
= f
= f
MCLK
MCLK
MCLK
B5
B5
0
0
/ 2).
/ 3).
/ 4).
B4
B4
0
Internal Clock Divide (IC(1:0))
Line Output Enable (LNOEN)
Charge-Pump Register
Line Input Enable (LNIEN)
B3
B3
DAC Enable (DACEN)
IC(1:0)
CP(4:0)
Clock Register
B2
B2
B1
B1
0
ICLK
B0
B0
0
=