SC16C754IB80,551 NXP Semiconductors, SC16C754IB80,551 Datasheet - Page 9

• Manufacturer Part Number: SC16C754IB80,551
• Description: IC UART QUAD W/FIFO 80-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C754IB80,551

• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3292; 935270057551; SC16C754IB80-S

Philips Semiconductors
9397 750 11618
Product data
Fig 4. Autoflow control (Auto-RTS and Auto-CTS) example.
D7-D0
6.2.1 Auto-RTS
FIFO
FIFO
RX
TX
With Auto-CTS, CTS must be active before the UART can transmit data.
Auto-RTS only activates the RTS output when there is enough room in the FIFO to
receive data and de-activates the RTS output when the RX FIFO is sufficiently full.
The halt and resume trigger levels in the TCR determine the levels at which RTS is
activated/deactivated.
If both Auto-CTS and Auto-RTS are enabled, when RTS is connected to CTS, data
transmission does not occur unless the receiver FIFO has empty space. Thus,
overrun errors are eliminated during hardware flow control. If not enabled, overrun
errors occur if the transmit data rate exceeds the receive FIFO servicing latency.
Auto-RTS data flow control originates in the receiver block (see
diagram.” on page
trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO
level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger
level is reached, RTS is deasserted. The sending device (e.g., another UART) may
send an additional byte after the trigger level is reached (assuming the sending UART
has another byte to send) because it may not recognize the deassertion of RTS until
it has begun sending the additional byte. RTS is automatically reasserted once the
receiver FIFO reaches the resume trigger level programmed via TCR[7:4]. This
reassertion allows the sending device to resume transmission.
UART 1
SERIAL-TO-
PARALLEL
PARALLEL-
TO-SERIAL
CONTROL
CONTROL
FLOW
FLOW
3).
Rev. 04 — 19 June 2003
RTS
CTS
RX
TX
Figure 5
shows RTS functional timing. The receiver FIFO
TX
CTS
RX
RTS
PARALLEL-
TO-SERIAL
SERIAL-TO-
PARALLEL
CONTROL
CONTROL
FLOW
FLOW
UART 2
Quad UART with 64-byte FIFO
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
FIFO
FIFO
RX
TX
SC16C754
Figure 1 “Block
002aaa228
D7-D0
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