SC16C754IB80,551 NXP Semiconductors, SC16C754IB80,551 Datasheet - Page 26

• Manufacturer Part Number: SC16C754IB80,551
• Description: IC UART QUAD W/FIFO 80-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C754IB80,551

• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3292; 935270057551; SC16C754IB80-S

Philips Semiconductors
9397 750 11618
Product data
7.6 Modem control register (MCR)
The MCR controls the interface with the mode, data set, or peripheral device that is
emulating the modem.
Table 14:
[1]
Bit
7
6
5
4
3
2
1
0
MCR[7:5] can only be modified when EFR[4] is set, i.e., EFR[4] is a write enable.
Symbol
MCR[7]
MCR[6]
MCR[5]
MCR[4]
MCR[3]
MCR[2]
MCR[1]
MCR[0]
Modem Control Register bits description
[1]
[1]
[1]
Rev. 04 — 19 June 2003
Description
Clock select.
TCR and TLR enable.
Xon Any.
Enable loop-back.
IRQ enable OP.
FIFO Ready enable.
RTS
DTR
Table 14
Logic 0 = Divide-by-1 clock input.
Logic 1 = Divide-by-4 clock input.
Logic 0 = no action.
Logic 1 = Enable access to the TCR and TLR registers.
Logic 0 = Disable Xon Any function.
Logic 1 = Enable Xon Any function.
Logic 0 = Normal operating mode.
Logic 1 = Enable local loop-back mode (internal). In this mode the
MCR[3:0] signals are looped back into MSR[7:4] and the TX output
is looped back to the RX input internally.
Logic 0 = Forces INTA-INTB outputs to the 3-State mode and OP
output to HIGH state.
Logic 1 = Forces the INTA-INTB outputs to the active state and OP
output to LOW state. In loop-back mode, controls MSR[7].
Logic 0 = Disable the FIFO Rdy register.
Logic 1 = Enable the FIFO Rdy register.
In loop-back mode, controls MSR[6].
Logic 0 = Force RTS output to inactive (HIGH).
Logic 1 = Force RTS output to active (LOW).
In loop-back mode, controls MSR[4]. If Auto-RTS is enabled, the
RTS output is controlled by hardware flow control.
Logic 0 = Force DTR output to inactive (HIGH).
Logic 1 = Force DTR output to active (LOW).
In loop-back mode, controls MSR[5].
shows modem control register bit settings.
Quad UART with 64-byte FIFO
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C754
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