SC16C754IB80,551 NXP Semiconductors, SC16C754IB80,551 Datasheet - Page 7

• Manufacturer Part Number: SC16C754IB80,551
• Description: IC UART QUAD W/FIFO 80-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C754IB80,551

• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3292; 935270057551; SC16C754IB80-S

Philips Semiconductors
Table 2:
9397 750 11618
Product data
Symbol
IOW
NC
RESET
RIA, RIB,
RIC, RID
RTSA, RTSB,
RTSC, RTSD
RXA, RXB,
RXC, RXD
RXRDY
TXA, TXB,
TXC, TCD
TXRDY
Pin description
Pin
LQFP80 PLCC68
11
1, 2, 20,
21, 22,
27, 40,
41, 42,
60, 61,
62, 80
33
78, 24,
38, 64
7, 15,
47, 55
77, 25,
37, 65
34
10, 12,
50, 52
35
…continued
18
31
37
8, 28,
42, 62
14, 22,
48, 56
7, 29,
41, 63
38
17, 19,
51, 53
39
Type
I
-
I
I
O
I
O
O
O
Description
Input/Output Write strobe (Active-LOW). A LOW-to-HIGH transition on
IOW will transfer the contents of the data bus (D0-D7) from the external
CPU to an internal register that is defined by address bits A0-A2 and CSA
and CSD.
Not connected.
Reset. This pin will reset the internal registers and all the outputs. The
UART transmitter output and the receiver input will be disabled during reset
time. RESET is an active-HIGH input.
Ring Indicator (Active-LOW). These inputs are associated with individual
UART channels, A through D. A logic 0 on these pins indicates the modem
has received a ringing signal from the telephone line. A LOW-to-HIGH
transition on these input pins generates a modem status interrupt, if
enabled. The state of these inputs is reflected in the modem status register
(MSR).
Request to Send (Active-LOW). These outputs are associated with
individual UART channels, A through D. A logic 0 on the RTS pin indicates
the transmitter has data ready and waiting to send. Writing a logic 1 in the
modem control register MCR[1] will set this pin to a logic 0, indicating data
is available. After a reset these pins are set to a logic 1. These pins only
affect the transmit and receive operations when Auto-RTS function is
enabled via the Enhanced Feature Register (EFR[6]) for hardware flow
control operation.
Receive data input. These inputs are associated with individual serial
channel data to the SC16C754. During the local loop-back mode, these RX
input pins are disabled and TX data is connected to the UART RX input
internally.
Receive Ready (Active-LOW). RXRDY contains the wire-ORed status of
all four receive channel FIFOs, RXRDY A-D. It goes LOW when the trigger
level has been reached or a time-out interrupt occurs. It goes HIGH when all
RX FIFOs are empty and there is an error in RX FIFO.
Transmit data. These outputs are associated with individual serial transmit
channel data from the SC16C754. During the local loop-back mode, the TX
output pin is disabled and TX data is internally connected to the UART RX
input.
Transmit Ready (Active-LOW). TXRDY contains the wire-ORed status of
all four transmit channel FIFOs, TXRDY A-D. It goes LOW when there are a
trigger level number of spaces available. It goes HIGH when all four TX
buffers are full.
Rev. 04 — 19 June 2003
Quad UART with 64-byte FIFO
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C754
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