XC56309PV100A Freescale Semiconductor, XC56309PV100A Datasheet - Page 87

• Manufacturer Part Number: XC56309PV100A
• Manufacturer: Freescale Semiconductor

Specifications of XC56309PV100A

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

4.3 Power Consumption Considerations
Power dissipation is a key issue in portable DSP applications. Some of the factors affecting current consumption
are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is
charging and discharging the capacitances of the pins and internal nodes.
Current consumption is described by this formula:
Where:
The maximum internal current (I
case operation conditions—not necessarily a real application case. The typical internal current (I
reflects the average switching of the internal buses on typical operating conditions.
Perform the following steps for applications that require very low current consumption:
Freescale Semiconductor
For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, with a 66 MHz clock, toggling at its maximum possible rate (33
MHz), the current consumption is expressed in Equation 4.
•
•
•
•
•
•
•
Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate
capacitance. This is especially critical in systems with higher capacitive loads that could create higher
transient currents in the
All inputs must be terminated (that is, not allowed to float) by CMOS levels except for the three pins with
internal pull-up resistors (
Take special care to minimize noise levels on the
The following pins must be asserted after power-up:
If multiple DSP devices are on the same board, check for cross-talk or excessive spikes on the supplies due
to synchronous operation of the devices.
RESET
deassertion of
At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip V
exceeds 3.5 V.
1.
2.
3.
4.
5.
Equation 3:
Equation 4:
Set the EBD bit when you are not accessing external memory.
Minimize external memory accesses, and use internal memory accesses.
Minimize the number of pins that are switching.
Minimize the capacitive load on the pins.
Connect the unused inputs to pull-up or pull-down resistors.
must be asserted when the chip is powered up. A stable
RESET
C
V
f
I
I
=
=
C
50
.
×
×
V
V
=
=
=
CCI
CC
TRST
10
×
f
–
max) value reflects the typical possible switching of the internal buses on best-
and
12
node/pin capacitance
voltage swing
frequency of node/pin toggle
Example 4-1. Current Consumption
×
,
TMS
GND
3.3
DSP56309 Technical Data, Rev. 7
×
,
circuits.
33
DE
×
).
10
6
=
5.48 mA
V
CCP
RESET
,
GND
P
and
, and
EXTAL
TRST
GND
.
signal should be supplied before
Power Consumption Considerations
P1
pins.
CCItyp
CC
) value
never
4-3