XC56309PV100A Freescale Semiconductor, XC56309PV100A Datasheet - Page 41

• Manufacturer Part Number: XC56309PV100A
• Manufacturer: Freescale Semiconductor

Specifications of XC56309PV100A

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
Notes:
No.
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
Random read or write cycle time
RAS assertion to data valid (read)
CAS assertion to data valid (read)
Column address valid to data valid (read)
CAS deassertion to data not valid (read hold time)
RAS deassertion to RAS assertion
RAS assertion pulse width
CAS assertion to RAS deassertion
RAS assertion to CAS deassertion
CAS assertion pulse width
RAS assertion to CAS assertion
RAS assertion to column address valid
CAS deassertion to RAS assertion
CAS deassertion pulse width
Row address valid to RAS assertion
RAS assertion to row address not valid
Column address valid to CAS assertion
CAS assertion to column address not valid
RAS assertion to column address not valid
Column address valid to RAS deassertion
WR deassertion to CAS assertion
CAS deassertion to WR
RAS deassertion to WR
CAS assertion to WR deassertion
RAS assertion to WR deassertion
WR assertion pulse width
WR assertion to RAS deassertion
WR assertion to CAS deassertion
Data valid to CAS assertion (write)
CAS assertion to data not valid (write)
RAS assertion to data not valid (write)
WR assertion to CAS assertion
CAS assertion to RAS assertion (refresh)
RAS deassertion to CAS assertion (refresh)
RD assertion to RAS deassertion
RD assertion to data valid
RD deassertion to data not valid
WR assertion to data active
WR deassertion to data high impedance
1.
2.
3.
4.
5.
The number of wait states for an out-of-page access is specified in the DRAM Control Register.
The refresh period is specified in the DRAM Control Register.
Use the expression to compute the maximum or minimum value listed (or both if the expression includes ±) .
Either t
RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t
Table 2-12.
RCH
or t
RRH
4
4
Characteristics
assertion
assertion
must be satisfied for read cycles.
DRAM Out-of-Page and Refresh Timings, Fifteen Wait States
5
DSP56309 Technical Data, Rev. 7
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WCH
WCR
t
WCS
t
RAC
CAC
t
RSH
CSH
RCD
RAD
CRP
t
RAH
CAH
t
RCS
RCH
RRH
RWL
CWL
t
t
DHR
CSR
RPC
ROH
t
t
t
OFF
RAS
CAS
ASR
ASC
RAL
WP
RC
AA
RP
CP
AR
DS
DH
GA
GZ
15.75 × T
14.25 × T
6.25 × T
1.75 × T
0.75 × T
Expression
8.25 × T
4.75 × T
6.25 × T
9.75 × T
6.25 × T
8.25 × T
4.75 × T
7.75 × T
6.25 × T
2.75 × T
0.75 × T
6.25 × T
9.75 × T
0.25 × T
15.5 × T
8.75 × T
6.25 × T
9.75 × T
4.75 × T
15.5 × T
5.5 × T
2.75 × T
9.5 × T
9.5 × T
1.5 × T
14 × T
3.5 × T
7 × T
5 × T
6 × T
0.25 × T
16 × T
0.0
C
C
C
C
C
C
C
C
C
C
C
OFF
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
− 4.0
− 3.8
− 4.2
C
C
C
− 5.7
− 5.7
− 4.2
− 4.3
− 4.0
C
– 3.7
– 1.5
− 5.7
− 5.7
− 4.0
− 4.0
− 4.0
− 4.0
− 4.0
− 4.0
– 6.0
− 4.0
− 4.0
− 4.0
− 4.0
− 4.0
− 2.0
− 4.5
− 4.0
− 4.0
− 4.0
− 4.0
− 4.0
± 2
± 2
− 4.3
− 4.3
C
AC Electrical Characteristics
and not t
3
1,2
GZ
160.0
150.5
153.2
138.2
151.0
Min
58.5
93.5
58.5
78.5
43.5
33.0
25.5
73.5
56.5
58.5
23.5
58.5
93.5
66.0
46.2
13.8
55.8
90.8
83.5
58.5
93.5
90.7
11.0
43.5
0.0
3.5
0.5
0.0
6.0
—
—
—
—
—
.
100 MHz
134.3
Max
76.8
41.8
49.3
37.0
29.5
2.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-21