XC56309PV100A Freescale Semiconductor, XC56309PV100A Datasheet - Page 11

• Manufacturer Part Number: XC56309PV100A
• Manufacturer: Freescale Semiconductor

Specifications of XC56309PV100A

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

1.6 Interrupt and Mode Control
The interrupt and mode control signals select the chip operating mode as it comes out of hardware reset. After
RESET is deasserted, these inputs are hardware interrupt request lines.
Freescale Semiconductor
RESET
MODA
IRQA
MODB
IRQB
MODC
IRQC
MODD
IRQD
Note: These signals are all 5 V tolerant.
Signal Name
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
Schmitt-trigger
Input
Schmitt-trigger
Input
Schmitt-trigger
Input
Schmitt-trigger
Input
Schmitt-trigger
Input
State During
Reset
Table 1-9.
DSP56309 Technical Data, Rev. 7
Reset—Places the chip in the Reset state and resets the internal phase
generator. The Schmitt-trigger input allows a slowly rising input (such as a
capacitor charging) to reset the chip reliably. When the RESET signal is
deasserted, the initial chip operating mode is latched from the MODA, MODB,
MODC, and MODD inputs. The RESET signal must be asserted after powerup.
Mode Select A—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET signal is deasserted.
External Interrupt Request A—After reset, this input becomes a level-
sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the STOP or WAIT standby
state and IRQA is asserted, the processor exits the STOP or WAIT state.
Mode Select B—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET signal is deasserted.
External Interrupt Request B—After reset, this input becomes a level-
sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the WAIT standby state and
IRQB is asserted, the processor exits the WAIT state.
Mode Select C—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET signal is deasserted.
External Interrupt Request C—After reset, this input becomes a level-
sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the WAIT standby state and
IRQC is asserted, the processor exits the WAIT state.
Mode Select D—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET signal is deasserted.
External Interrupt Request D—After reset, this input becomes a level-
sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the WAIT standby state and
IRQD is asserted, the processor exits the WAIT state.
Interrupt and Mode Control
Signal Description
Interrupt and Mode Control
1-7