NS16C2552TVS/NOPB National Semiconductor, NS16C2552TVS/NOPB Datasheet - Page 12

• Manufacturer Part Number: NS16C2552TVS/NOPB
• Description: IC UART DUAL 16BYTE 48-TQFP
• Manufacturer: National Semiconductor

Specifications of NS16C2552TVS/NOPB

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NS16C2552TVS

www.national.com
Bit
7
6
5
4
3
2
1
0
6.2 TRANSMIT HOLDING REGISTER (THR)
This register holds the byte-wide transmit data (THR). This is
a write-only register.
6.3 INTERRUPT ENABLE REGISTER (IER)
This register enables eight types of interrupts for the corre-
sponding serial channel. Each interrupt source can individu-
ally activate the interrupt (INTR) output signal. Setting the bits
of the IER to a logic 1 unmasks the selected interrupt(s). Sim-
ilarly, the interrupt can be masked off by resetting bits 0
6.4 INTERRUPT IDENTIFICATION REGISTER (IIR)
In order to provide minimum software overhead during data
word transfers, each serial channel of the DUART prioritizes
interrupts into seven levels and records these levels in the
Interrupt Identification Register. The seven levels of interrupt
conditions are listed in Table 7. When the CPU reads the IIR,
Rx Line Stat Int
Rx_DV Int Ena
Tx_Empty Int
Mdm Stat Int
CTS Int Ena
RTS Int Ena
Sleep Mode
Xoff Int Ena
Bit
7:0
Bit Name
Ena
Ena
Ena
Ena
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Def
THR Data
Bit Name
0
0
0
0
0
0
0
0
CTS Input Interrupt Enable
1 = Enable the CTS to generate interrupt at low to high transition. Requires EFR 0x2.4 = 1.
0 = Disable the CTS interrupt (default).
RTS Output Interrupt Enable
1 = Enable the RTS to generate interrupt at low to high transition. Requires EFR 0x2.4 = 1.
0 = Disable the RTS interrupt (default).
Xoff Input Interrupt Enable
1 = Enable the software flow control character Xoff to generate interrupt. Requires EFR 0x2.4 = 1.
0 = Disable the Xoff interrupt (default).
Sleep Mode Enable
1 = Enable the Sleep Mode for the respective channel. Requires EFR 0x2.4 = 1.
0 = Disable Sleep Mode (default).
Modem Status Interrupt Enable
1 = Enable the Modem Status Register interrupt.
0 = Disable the Modem Status Register interrupt (default).
Receive Line Status Interrupt Enable
An interrupt can be generated when any of the LSR bits 0x5.4:1=1. LSR 0x5.1 generates an interrupt
as soon as an overflow frame is received. LSR 0x5.4:2 generate an interrupt when there is read error
from FIFO.
1 = Enable the receive line status interrupt.
0 = Disable the receive line status interrupt (default).
Tx Holding Reg Empty Interrupt Enable
1 = Enable the interrupt when Tx Holding Register is empty.
0 = Disable the Tx Holding Register from generating interrupt (default).
Rx Data Available Interrupt Enable
1 = Enable the Received Data Available and FIFO mode time-out interrupt.
0 = Disable the Received Data Available interrupt (default).
R/W Def
0xXX
W
TABLE 4. THR (0x0)
TABLE 5. IER (0x1)
Transmit Holding Register
Tx FIFO data.
Note: This register value does not change upon MR reset.
12
through 7 of the Interrupt Enable Register (IER). If not desired
to be used, masking an interrupt source prevents it from going
active in the IIR and activating the INTR output signal. While
interrupt sources are masked off, all system functions includ-
ing the Line Status and MODEM Status still operate in their
normal manner. Table 5 shows the contents of the IER.
the associated DUART serial channel freezes all interrupts
and indicates the highest priority pending interrupt to the
CPU. While this CPU access is occurring, the associated
DUART serial channel records new interrupts, but does not
change its current indication until the access is complete. Ta-
ble 6 shows the contents of the IIR.
Description
Description