DSP-DEVKIT-2S60 Altera, DSP-DEVKIT-2S60 Datasheet - Page 26

• Manufacturer Part Number: DSP-DEVKIT-2S60
• Manufacturer: Altera

Specifications of DSP-DEVKIT-2S60

• Lead Free Status / Rohs Status: Not Compliant

Board Components
2–16
Stratix II Development Board
SRAM Memory (U43 & U44)
U43 and U44 are two 256 Kbyte x 16-bit asynchronous SRAM devices.
They are connected to the Stratix II device so they can be used by a
Nios
devices can be used in parallel to implement a 32-bit wide memory
subsystem. Refer to
devices U43 and U44.
Note to
(1)
dacB_D1 (MSB)
dacB_D2
dacB_D3
dacB_D4
dacB_D5
dacB_D6
dacB_D7
dacB_D8
dacB_D9
dacB_D10
dacB_D11
dacB_D12
dacB_D13
dacB_D14 (LSB)
SE_A0
SE_A1
SE_A2
SE_A3
SE_A4
SE_A5
Table 16. D/A B (U15, J17) Stratix II Pin-Outs
Table 17. SRAM Memory (U43 & U44) (Part 1 of 3)
®
The Texas Instruments (TI) naming conventions differ from those of Altera
Corporation. The TI data sheet for the DAC 904 D/A converter lists bit 1 as the
most significant bit (MSB) and bit 14 as the least significant bit (LSB).
II embedded processor as general-purpose memory. The two 16-bit
Signal Name
Table
Pin Name
16:
Reference Manual
(1)
Table 17
for Stratix II device pin-outs for SRAM
Pin Number
AM27
AM28
AK27
AJ27
AL29
AD8
Stratix II Pin
AA10
AA11
Y10
Y11
AB5
AB6
AA6
AA7
W4
W5
Y6
Y7
Y8
Y9
Altera Corporation
August 2006