DSP-DEVKIT-2S60 Altera, DSP-DEVKIT-2S60 Datasheet - Page 17

• Manufacturer Part Number: DSP-DEVKIT-2S60
• Manufacturer: Altera

Specifications of DSP-DEVKIT-2S60

• Lead Free Status / Rohs Status: Not Compliant

Board Components & Interfaces
Board
Components
Altera Corporation
August 2006
Notes to
(1)
(2)
(3)
ALMs
Adaptive look-up tables (ALUTs)
Equivalent LEs
M512 RAM Blocks (32 × 18 bits)
M4K RAM Blocks (128 × 36 bits)
M-RAM Blocks
Total RAM bits
DSP Blocks
18-bit × 18-bit multipliers
Enhanced PLLs
Fast PLLs
Maximum user I/O pins
Package type
Board reference
Voltage
Table 5. Stratix II Device Features
One ALM contains two ALUTs. The ALUT is the cell used in the Quartus II software for logic synthesis.
This is the equivalent number of LEs in a Stratix device (four-input LUT-based architecture).
These multipliers are implemented using the DSP blocks.
Table
5:
(2)
f
Feature
(3)
The following sections describe the development board components.
Stratix II Device (U18)
The Stratix II EP2S60 device on the board features 24,176 adaptive logic
modules (ALMs) in a speed grade (-3) 1,020-pin FineLine BGA
The device has 2,544,192 total RAM bits.
The Stratix II EP2S180 device on the board features 71,760 adaptive logic
modules (ALMs) in a speed grade (-3) 1,020-pin FineLine BGA package.
The device has 9,383,040 total RAM bits.
For more information on Stratix II devices, refer to the Stratix II Device
Handbook.
Table 5
EP2S180F1020C3 devices.
(1)
describes the features of the Stratix II EP2S60F1020C4 and
Reference Manual
24,176
48,352
60,440
329
255
2
2,544,192
36
144
4
8
717
1,020-pin FineLine BGA
U18
1.2 V (internal), 3.3 V (I/O)
EP2S60F1020
71,760
143,520
179,400
930
768
9
9,383,040
96
384
4
8
743
1,020-pin FineLine BGA
U15
1.2 V (internal), 3.3 V (I/O)
Stratix II Development Board
EP2S180F1020C3
®
package.
2–7