DSP-DEVKIT-2S60 Altera, DSP-DEVKIT-2S60 Datasheet
DSP-DEVKIT-2S60
Specifications of DSP-DEVKIT-2S60
DSP-DEVKIT-2S60 Summary of contents
Page 1
... Stratix II DSP Development Board 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.com Reference Manual Document Version: Document Date: 6.0.1 August 2006 ...
Page 2
... Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in- formation and before placing orders for products or services ii Stratix II DSP Development Board . MNL-01003-1.0 Reference Manual ...
Page 3
... About this Manual Revision History ........................................................................................................................................ v How to Contact Altera .............................................................................................................................. v Typographic Conventions ...................................................................................................................... vi Chapter 1. Introduction General Description ............................................................................................................................... 1–1 Board Components .......................................................................................................................... 1–1 Debugging Interfaces ....................................................................................................................... 1–2 Expansion Interfaces ........................................................................................................................ 1–2 Block Diagram .................................................................................................................................. 1–3 Environmental Requirements .............................................................................................................. 1–3 Handling the Board ............................................................................................................................... 1–4 Chapter 2. Board Components & Interfaces Board Overview ..................................................................................................................................... 2–1 Power ................................................................................................................................................. 2– ...
Page 4
... Configure the Stratix II Device Directly ........................................................................................ 3–2 Non-Volatile Configuration ................................................................................................................. 3–2 Configuration Data .......................................................................................................................... 3–3 Factory & User Configurations ...................................................................................................... 3–4 The Factory Design .......................................................................................................................... 3–5 Install or Remove the Active Heat Sink ............................................................................................. 3–5 Remove the Active Heat Sink ......................................................................................................... 3–6 iv Stratix II Development Board Reference Manual Altera Corporation August 2006 ...
Page 5
... This document provides information about the Altera of devices and the Stratix II DSP development board. f Refer to the readme file or user guide on the DSP Development Kit, Stratix II Edition Version 6.0.1 CD-ROM for additional information. How to Contact For technical support or other information about Altera products the Altera world-wide web site at www ...
Page 6
... The feet direct you to more information on a particular topic. 2–vi Stratix II Development Board Meaning , Active-low signals are denoted by suffix input. c:\qdesigns\tutorial\chiptrip.gdf ), as well as logic function names (e.g., SUBDESIGN Reference Manual , data1 , e.g resetn . Also, sections are shown in TRI Altera Corporation August 2006 ...
Page 7
... General The Altera Development Kit, Stratix II Edition (ordering codes DSP-DEVKIT-2S60 Description and DSP-DEVKIT-2S180). This board is a development platform for high-performance digital signal processing (DSP) designs, and features the Stratix II EP2S60/EP2S180 device in a 1,020-pin package. The Stratix II DSP development board provides a hardware platform that designers can use to start developing DSP systems based on Stratix II devices ...
Page 8
... Active heat sink One Mictor-type connector for Agilent and Tektronix logic analyzers Several 0.1-inch headers Two connectors for Analog Devices A/D converter daughter cards Connector for Texas Instruments Evaluation Module (TI-EVM) daughter cards Two Expansion Prototype connectors Reference Manual Altera Corporation August 2006 ...
Page 9
... C and 100° C. The recommended operating temperature is between Requirements 0° C and 55° The DSP Development Kit, Stratix II Edition includes a heat sink and fan combination, also known as an active heat sink. Depending on the specific requirements of your application, this level of cooling may not be necessary. Refer to page 3–5 ...
Page 10
... When handling the board important to observe the following precaution: Board w 1–4 Stratix II Development Board Without proper anti-static handling, you can damage the board. Therefore, use the proper anti-static handling precautions when touching the board. Reference Manual Altera Corporation August 2006 ...
Page 11
... For detailed part numbers and manufacturers, refer to the information provided in the BoardDesignFiles directory. Figure 1 Figure 1. Stratix II DSP Development Board Components & Interfaces External Clock Inputs (J10, J11) VGA Connector (J35) 40-Pin Connectors for Analog Devices A/D Converters (J5, J6) ...
Page 12
... Board Overview Table 1 supports. Table 1. Stratix II DSP Development Board Components & Interfaces (Part Component/ Type Interface Components ® FPGA Stratix II device PLD ® MAX Device A/D converters I/O D/A converters I/O 1 MByte SRAM Memory 16 MBytes of flash Memory memory 32 MBytes of Memory SDRAM ...
Page 13
... Board Components & Interfaces Table 1. Stratix II DSP Development Board Components & Interfaces (Part Component/ Type Interface VGA D/A Converter I/O Audio CODEC I/O CompactFlash card I/O connector Debugging Interfaces Mictor connectors I/O Expansion Interfaces Analog Devices Expansion connector (1) TI-EVM connectors Expansion ...
Page 14
... Board Overview Table 2 connects from the wall socket to the DSP development board. Table 2. Power Supply Specifications Board reference Device description Clocks & Clock Distribution Table 3 Table 3. Clock Distribution Signals (Part Signal Name dac_PLLCLK1 dac_PLLCLK1_n dac_PLLCLK2 dac_PLLCLK2_n sdram_CLK adc_PLLCLK1 adc_PLLCLK2 audio_CLK pld_MICTORCLK ...
Page 15
... J3 and J4 control which clock is routed to the A/D converters. See (2) J18 and J19 control which clock is routed to the D/A converters. See The Stratix II DSP development board can obtain a clock source from one or more of the following sources: ■ ■ The board can provide independent clocks from both the enhanced and fast PLLs to the A/D converters, the D/A converters, and the other components that require stable clock sources ...
Page 16
... Make sure to note the correct orientation of the oscillator before removing it. Reference Manual Expansion Prototype Connector Clock Expansion 2 Prototype Connector SDRAM Audio CODEC CLK ADC A Buffer CLK ADC B Buffer DAC DAC Altera Corporation August 2006 ...
Page 17
... One ALM contains two ALUTs. The ALUT is the cell used in the Quartus II software for logic synthesis. (2) This is the equivalent number of LEs in a Stratix device (four-input LUT-based architecture). (3) These multipliers are implemented using the DSP blocks. Altera Corporation August 2006 describes the features of the Stratix II EP2S60F1020C4 and ...
Page 18
... Stratix II device. This LED turns on when the factory configuration is being transferred from flash memory and stays illuminated if the factory configuration was successfully loaded into the Stratix II device. Reference Manual Altera Corporation August 2006 ...
Page 19
... D1) pld_LED1 (board designation: D2) pld_LED2 (board designation: D3) pld_LED3 (board designation: D4) pld_LED4 (board designation: D5) pld_LED5 (board designation: D6) pld_LED6 (board designation: D7) pld_LED7 (board designation: D8) Altera Corporation August 2006 shows the pin-outs for the seven-segment display and LEDs. Signal Reference Manual Stratix II Pin C4 C5 ...
Page 20
... Figure 3 Figure 3. Pin-Out Diagram for the Dual Seven-Segment Display A/D Converters The Stratix II DSP development board has two 12-bit A/D converters that produce samples at a maximum rate of 125 mega-samples per second (MSPS). The A/D subsystem of the board has the following features: ■ ...
Page 21
... Table 9. A/D Clock Source Settings Pins 1 and 2 Pins 3 and 4 Pins 5 and 6 Table 10 Table 10. A/D Converter Reference Board reference Device description Voltage Altera Corporation August 2006 Table 9 J3, J4 Setting Clock Source Stratix II PLL circuitry OSC or External input clock positive OSC or External input clock negative lists reference information for the A/D converters ...
Page 22
... Stratix II Development Board and 12 show the ADC A (U1) and ADC B (U2) Stratix II Signal Name Stratix II Pin Signal Name Stratix II Pin Reference Manual Altera Corporation August 2006 ...
Page 23
... D/A converter chip, DAC904, consists of a current source whose maximum value is 20 mA. This differential output is converted to a single -ended output using an RF transformer The DSP board uses a 1:1 ratio transformer to interface ohm impedance load. Each of the outputs is terminated with a 49.9 ohm resistor to ground. This circuit results in outputs being AC coupled and inherently isolated due to transformer’ ...
Page 24
... D/A converters. Clock Source Stratix II PLL Circuitry Stratix II PLL Circuitry OSC or External input clock (J10) External input clock (J12) DA EXT CLK dac_DACCLKIN1, Reference Manual Description , 5.0-V analog Signal Name dac_PLLCLK1, dac_PLLCLK2 dac_PLLCLK1_n, dac_PLLCLK2_n dac_CLK_IN1, dac_CLK_IN2 dac_DACCLKIN2 Altera Corporation August 2006 ...
Page 25
... Table 15. D/A A (U14, J15) Stratix II Pin-Outs dacA_D1 (MSB) dacA_D2 dacA_D3 dacA_D4 dacA_D5 dacA_D6 dacA_D7 dacA_D8 dacA_D9 dacA_D10 dacA_D11 dacA_D12 dacA_D13 dacA_D14 (LSB) Altera Corporation August 2006 and 16 show the DAC A (U14) and DAC B (U15) Stratix II Signal Name Stratix II Pin U5 U6 U10 U11 V9 V10 V6 V7 ...
Page 26
... Signal Name (1) Table 16: The Texas Instruments (TI) naming conventions differ from those of Altera Corporation. The TI data sheet for the DAC 904 D/A converter lists bit 1 as the most significant bit (MSB) and bit 14 as the least significant bit (LSB). ® II embedded processor as general-purpose memory. The two 16-bit ...
Page 27
... SE_D2 SE_D3 SE_D4 SE_D5 SE_D6 SE_D7 SE_D8 SE_D9 SE_D10 SE_D11 SE_D12 SE_D13 SE_D14 SE_D15 SE_D16 SE_D17 SE_D18 SE_D19 Altera Corporation August 2006 Pin Name Pin Number AM29 AJ28 AH28 AK20 AJ20 AL21 AL22 AJ22 AH22 AL23 AL24 AJ25 AH25 AL25 AD18 ...
Page 28
... Pin Number AC18 AB17 AC19 AL26 AL27 AL28 AK28 AK29 AC13 AD10 AC11 AE11 AG11 AK10 AK11 AL11 AL12 AG14 AH14 lists the reference information for the SRAM memory. Item U43, U44 SRAM Memory Reference Manual Description Altera Corporation August 2006 ...
Page 29
... Embedded Processor Windows, version 6.0 CD-ROM included in your kit, and use the Nios II IDE Flash Programmer. To use the Flash Programmer with the DSP board, you must specify an SOPC Builder setting that locates a board description file for the DSP board. Perform the following: 1 ...
Page 30
... Pin Name Pin Number AF30 AF29 AE30 AE29 AG32 AG31 AF32 AF31 AE32 AE31 AD32 AD31 AB28 AB27 AC32 AC31 AB30 AB29 Y29 Y28 AA30 AA29 AB32 AB31 AH30 AH29 AJ32 AJ31 AG30 AG29 AH32 AH31 Reference Manual Altera Corporation August 2006 ...
Page 31
... The SDRAM is fully synchronous with all signals registered on the positive edge of the system clock. The SDRAM device pins are connected to the Stratix II device. An SDRAM controller peripheral is included with the Stratix II DSP Development Kit, allowing a Nios II processor to view the SDRAM devices as a large, linearly-addressable memory. ...
Page 32
... Reference Manual AB15 AC16 AB16 AE13 AL9 AF11 AL4 AJ5 AH5 AM4 AG9 AH6 AH7 AH9 AM5 AK6 AJ6 AM6 AM7 AK7 AJ7 AM8 AJ10 AK8 AJ8 AM9 AF12 AG10 AF10 AG12 AJ11 AH11 AL10 AM10 Altera Corporation August 2006 ...
Page 33
... CKE CS_N WE_N CLK Table 22 Table 22. SDRAM Device (U40) Pin-Outs (Part A10 A11 BA0 BA1 DQ0 Altera Corporation August 2006 Pin Name Pin Number Connects to Stratix II Pin lists the Stratix II device pin-outs for SDRAM device U40. Pin Name Pin Number Connects to Stratix II Pin ...
Page 34
... Reference Manual AG13 AF13 AG15 AL14 AJ14 AJ13 AM14 AL20 AH19 AJ19 AH20 AM21 AK21 AJ21 AM22 AJ23 AK22 AG22 AG23 AM23 AK23 AK24 AM24 AK25 AH24 AH26 AG24 AM26 AM25 AJ26 AK26 AK13 AL13 AB12 Altera Corporation August 2006 ...
Page 35
... Table 24 Table 24. Ethernet MAC/PHY (U16) (Part ENET_ADS_N ENET_AEN ENET_BE_N0 ENET_BE_N1 ENET_BE_N2 ENET_BE_N3 ENET_DATACS_N ENET_INTRQ0 ENET_IOCHRDY ENET_IOR_N ENET_IOW_N Altera Corporation August 2006 Pin Name Pin Number Connects to Stratix II Pin lists the reference information for the SDRAM memory. Item U39, U40 SDRAM Memory for Stratix II pin-outs for Ethernet MAC/PHY device U16 ...
Page 36
... Pin Number T26 T25 T21 AD8 AM27 AM28 AJ27 AK27 AL29 AM29 AJ28 AH28 AK20 AJ20 AL21 AL22 AJ22 AH22 AL23 AL24 AJ25 AH25 AL25 AD18 AB18 AB19 AC20 AD20 AE20 AB20 AF20 AC21 AD21 Reference Manual Altera Corporation August 2006 ...
Page 37
... SE_D20 SE_D21 SE_D22 SE_D23 SE_D24 SE_D25 SE_D26 SE_D27 SE_D28 SE_D29 SE_D30 SE_D31 Table 25 Table 25. Ethernet MAC/PHY Reference Board reference Device description Altera Corporation August 2006 Pin Name Pin Number AB21 AE21 AG20 AF21 AD22 AF22 AE22 AC17 AE19 AD19 AC18 AB17 ...
Page 38
... FPGA does not drive this signal directly. provides CompactFlash pin-out details. CompactFlash Function (CON1) (U60) GND D03 D04 D05 D06 D07 CS0# A10 ATA_SEL# A09 A08 A07 VCC Reference Manual Connects to (1) GND AA3 AA1 AE3 AF1 AD12 AF3 AF4 AG1 ( Altera Corporation August 2006 ...
Page 39
... Table 26. CompactFlash (CON1) Pin Table (Part Pin on CompactFlash Altera Corporation August 2006 CompactFlash Function (CON1) (U60) A06 A05 A04 A03 A02 A01 A00 DO0 DO1 DO2 IOCS16# CD2# CD1# D11 D12 D13 D14 D15 CS1# VS1# IORD# IOWR# WE# INTRQ VCC CSEL# VS2# RESET (4) WAIT# ...
Page 40
... This pin does not connect to the FPGA directly. RESET is driven by the EPM7256AE configuration controller device. lists the reference information for the CompactFlash connector. Item Description CON1 CompactFlash connector shows an example of an in-target system analyzer ISA-Nios/T Reference Manual Connects to ( (3) GND to CON1. CC Altera Corporation August 2006 ...
Page 41
... Figure 6 Stratix II device. noted, labels indicate Stratix II device pin numbers. Figure 6. Mictor Connector Signaling Figure 7. Debug Mictor Connector - J20 Altera Corporation August 2006 J25 below shows connections from the Mictor connector to the Figure 7 shows the pin-out for J20. Unless otherwise ...
Page 42
... LSB linearity error Internal bandgap voltage reference Low glitch energy Single 3.3-V power supply shows the pin-outs for the VGA interface. Signal Reference Manual Stratix II Pin E11 G10 G11 G12 D12 A11 B11 Altera Corporation August 2006 ...
Page 43
... The stereo jacks are driven by a Stereo Audio CODEC running at 8-96 KHz. Table 31. Audio CODEC (U5) Pin-Outs (Part audio_BCLK audio_CS_n Altera Corporation August 2006 Signal Stratix II Pin describes the device used to implement the VGA interface. Item ...
Page 44
... Table 32 Table 32. Audio CODEC Device Reference Board reference Device description Voltage Expansion The Stratix II DSP development board includes the following interfaces: Interfaces ■ ■ ■ ■ TI-EVM/FPDP Connector (J31, J33) The TI-EVM interface is specifically designed to work with TI boards that have the EVM interface ...
Page 45
... Altera Corporation August 2006 lists the pin-outs for the TI-EVM and FPDP connectors. TI-EVM Signal Name Reference Manual Stratix II Pin J21 H22 K12 H13 L12 J12 H12 K11 ...
Page 46
... Reference Manual Stratix II Pin C23 C24 A24 A25 A26 D26 C26 E24 C25 E27 E26 A27 A28 D27 C27 B29 A29 D28 E28 D19 B21 D22 B23 B25 D25 B27 C28 D20 B22 E22 B24 B26 E25 B28 Altera Corporation August 2006 ...
Page 47
... J29’s RXD and TXD. LEDs are connected to the RXD and TXD signals, giving a visual indication when data is being transmitted or received. serial connector and the Stratix II device. Altera Corporation August 2006 TI-EVM Signal Name Table 35 describes the device used to implement the ...
Page 48
... RS-232C transciever device. Item Description U41 RS-232 transceiver 3.3 V Reference Manual GND DTR1 RXD1 TXD1 DCD1 IN IN OUT OUT K13 L16 L17 H14 K17 K15 L15 K16 OUT OUT IN OUT RI1 CTS1 RTS1 DSR1 Altera Corporation August 2006 ...
Page 49
... Board Components & Interfaces Analog Devices Corporation External A/D Support The Stratix II DSP development board supports Analog Devices A/D converters via two 40-pin 0.1-inch digital I/O headers (J5, J6). These two dual-purpose digital I/O headers can support a maximum of the following three converters. ...
Page 50
... Headers J23, J24, and J25 collectively form a standard-footprint, mechanically-stable connection that can be used (for example interface to a special-function daughter card. f For a list of available expansion daughter cards that can be used with the Stratix II DSP development board refer to www.altera.com/devkits. The expansion prototype connector interfaces include: ■ ■ ■ ...
Page 51
... Figure 10. Expansion Prototype Connector Pin Information - J23, J24, J25 Notes to Figure 10: (1) Unregulated voltage from power transformer (2) Clk from board oscillator (3) Clk from the Stratix II device via buffer (4) Clk output from the card to the Stratix II device Altera Corporation August 2006 J23 Pin 1 J25 J24 Pin 1 Pin 1 RESET_n 1 R31 3 ...
Page 52
... Five regulated 3.3-V power-supply pins (2A total max load for both expansion prototype connectors). One regulated 5-V power-supply pin (1A total max load for both expansion prototype connectors). Numerous ground connections. and 12 show connections from the expansion prototype to the J27 Pin 1 J26 Pin 1 Reference Manual J28 Pin 1 Altera Corporation August 2006 ...
Page 53
... Figure 12. Expansion Prototype Connector -Pin Information for J26, J27, & J28 Notes to Figure 12: (1) Unregulated voltage from power transformer (2) Clk from board oscillator (3) Clk from the Stratix II device via buffer (4) Clk output from card connected to the Stratix II device. Altera Corporation August 2006 RESET_n 1 AC27 3 AD27 5 Y23 7 Y25 9 ...
Page 54
... Expansion Interfaces 2–44 Stratix II Development Board Reference Manual Altera Corporation August 2006 ...
Page 55
... Apply Power Apply power to the board by connecting the 16-V DC power supply adapter, provided in the DSP Development Kit, Stratix II edition, to the on-board power adapter connector (J22), and switching SW9 to the ON position. All of the board components draw power either directly from this 16-V supply or from the 3.3-V, 1.2-V, and 5-V regulators that are powered by the 16-V supply ...
Page 56
... Non-Volatile The designer must reconfigure the Stratix II device each time power is applied to the Stratix II DSP development board. For designers who want Configuration to power up the board and have a design immediately present in the Stratix II device, the board has a non-volatile configuration scheme. This scheme consists of a configuration controller (U10), which is an Altera EPM7256 PLD, and flash memory ...
Page 57
... Quartus II software Altera Corporation August 2006 Create a HEXOUT file at the end of compilation Convert a SRAM Object File (.sof HEXOUT file. Choose Settings (Assignments menu). Click Device under Compiler Settings. Click Device and Pin Options. Click the Programming Files tab. ...
Page 58
... RS-232 cable and write it to flash memory by the factory configuration as described in the next section. “Non-Volatile Configuration” on page 3–2 On the Stratix II EP2S180 DSP board, only the factory image and User0 are available because of the size of the configuration files for the EP2S180 device. Image ...
Page 59
... DSP Development Kit, Stratix II Edition Getting Started User Guide. Install or The DSP Development Kit, Stratix II Edition includes a heat sink and fan combination, also known as an active heat sink. This active heat sink Remove the maintains the Stratix II device within its thermal operating range, ...
Page 60
... Pry the thermal tape loose and remove the heat sink from the device. Do not pull the heat sink off of the Stratix II device because this action may cause the device to break off of the board. Always pry the heat sink off. Reference Manual Altera Corporation August 2006 ...