MAX3107ETG+ Maxim Integrated Products, MAX3107ETG+ Datasheet - Page 48

• Manufacturer Part Number: MAX3107ETG+
• Description: IC UART SPI/I2C 128 FIFO 24TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX3107ETG+

• Features: Internal Oscillators
• Number Of Channels: 4, QUART
• Fifo's: 128 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.35 V ~ 3.6 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-TQFN Exposed Pad
• Data Rate: 24 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 2.35 V
• Supply Current: 0.64 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• No. Of Channels: 1
• Uart Features: 128-Word Transmit / Receive FIFO, Half-Duplex Echo Suppression, Shutdown And Autosleep Modes
• Supply Voltage Range: 2.35V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 23. Startup and Initialization Flowchart
SPI/I
and Internal Oscillator
To reduce the power consumption during normal opera-
tion, the following techniques can be adopted:
• Do not use the internal PLL. This saves the most power
• Use an external clock source. Of the three clocking
• Keep the internal clock rates as low as possible.
• Use low voltage on the V
• Use an external 1.8V supply. This saves the power
48
of the options listed here. Disable and bypass the PLL.
With the PLL enabled, the current to the V
in the range of a few mA (depending on clock and
multiplication factor), while it drops to below 1mA if
disabled.
sources, the internal oscillator consumes the most
power (about double that when using an external
crystal).
dissipated in the internal 1.8V linear regulator for the
1.8V logic supply. Connect the external 1.8V supply to
V
LDOEN to DGND.
18
_____________________________________________________________________________________
and disable the internal regulator by connecting
2
C UART with 128-Word FIFOs
RST INPUT PULLED HIGH/
RST BIT SET LOW
SUCCESSFULLY
IS IRQ HIGH?
POWER-UP/
RevID READ
CONFIGURE
CONFIGURE
CLOCKING
MODES
OR
A
Low-Power Operation
Y
supply.
N
A
supply is
The host controller can manage and control the MAX3107
through polling and/or through interrupts. In polled
mode, the IRQ physical interrupt output is not used and
the host controller polls the ISR register at frequent inter-
vals to establish the state of the MAX3107.
Alternatively, the MAX3107’s physical IRQ interrupt
can be used to interrupt the host controller at specified
events, making polling unnecessary. The IRQ output is
an open-drain output that requires a pullup resistor to V
The MAX3107 can be directly connected to transceivers
and controllers that have different supply voltages. The
V
ler interface while the V
the transceiver interface. This ensures flexibility when
selecting a controller and transceiver. Figure 24 is an
example of a setup when the controller, transceiver, and
the MAX3107 are powered by three different supplies.
L
input defines the logic voltage levels of the control-
COMMUNICATION
FLOW CONTROL
FIFO CONTROL
INTERRUPTS
CONFIGURE
CONFIGURE
CONFIGURE
ENABLE
START
GPIOs
EXT
Logic-Level Translation
Interrupts and Polling
voltage defines the logic of
L
.