MAX3107ETG+ Maxim Integrated Products, MAX3107ETG+ Datasheet - Page 36

• Manufacturer Part Number: MAX3107ETG+
• Description: IC UART SPI/I2C 128 FIFO 24TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX3107ETG+

• Features: Internal Oscillators
• Number Of Channels: 4, QUART
• Fifo's: 128 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.35 V ~ 3.6 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-TQFN Exposed Pad
• Data Rate: 24 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 2.35 V
• Supply Current: 0.64 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• No. Of Channels: 1
• Uart Features: 128-Word Transmit / Receive FIFO, Half-Duplex Echo Suppression, Shutdown And Autosleep Modes
• Supply Voltage Range: 2.35V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIFOTrgLvl—FIFO Interrupt Trigger Level Register
TxFIFOLvl—Transmit FIFO Level Register
RxFIFOLvl—Receive FIFO Level Register
SPI/I
and Internal Oscillator
Bits 7–4: RxTrig[3:0]
These 4 bits allow definition of the receive FIFO threshold level at which an ISR[3] interrupt is generated. This can be
used to signal that the receive FIFO is nearing overflow or that a predefined number of FIFO locations are available for
being read out in one block.
The actual FIFO trigger level is 8 times RxTrig[7:4], hence, the selectable threshold granularity is eight.
Bits 3–0: TxTrig[3:0]
These 4 bits allow definition of the transmit FIFO threshold level at which the MAX3107 generates an ISR[4] interrupt.
This can be used to manage data flow to the transmit FIFO. For example, if the trigger level is defined near the bottom
of the TxFIFO, the host knows that a predefined number of FIFO locations are available for being written to in one block.
Alternatively, if the trigger level is set near the top of the FIFO, the host is warned when the transmit FIFO is nearing
overflow, if written to on a word-by-word basis.
The actual FIFO trigger level is 8 times TxTrig[3:0], hence, the selectable threshold granularity is eight.
Bits 7–0: TxFL[7:0]
The TxFIFOLvl register represents the current number of words in the transmit FIFO.
Bits 7–0: RxFL[7:0]
The RxFIFOLvl register represents the current number of words in the receive FIFO.
36
ADDRESS:
MODE:
ADDRESS:
MODE:
ADDRESS:
MODE:
RESET
RESET
RESET
NAME
NAME
NAME
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BIT
BIT
BIT
2
C UART with 128-Word FIFOs
RxTrig3
RxFL7
TxFL7
7
1
7
0
7
0
0x10
R/W
0x11
R
0x12
R
RxTrig2
RxFL6
TxFL6
6
1
6
0
6
0
RxTrig1
RxFL5
TxFL5
5
1
5
0
5
0
RxTrig0
RxFL4
TxFL4
4
1
4
0
4
0
TxTrig3
RxFL3
TxFL3
3
1
3
0
3
0
TxTrig2
RxFL2
TxFL2
2
1
2
0
2
0
TxTrig1
RxFL1
TxFL1
1
1
1
0
1
0
TxTrig0
RxFL0
TxFL0
0
1
0
0
0
0