SC16IS740IPW,112 NXP Semiconductors, SC16IS740IPW,112 Datasheet - Page 20

• Manufacturer Part Number: SC16IS740IPW,112
• Description: IC UART SINGLE W/FIFO 16-TSSOP
• Manufacturer: NXP Semiconductors
• Type: UART with 64-byte FIFOs and IrDA encoder/decoderr

Specifications of SC16IS740IPW,112

• Number Of Channels: 1, UART
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3648-5; 935280988112; SC16IS740IPW

NXP Semiconductors
8. Register descriptions
SC16IS740_750_760_6
Product data sheet
The programming combinations for register selection are shown in
Table 9.
[1]
[2]
[3]
[4]
[5]
Register name Read mode
RHR/THR
IER
IIR/FCR
LCR
MCR
LSR
MSR
SPR
TCR
TLR
TXLVL
RXLVL
IODir
IOState
IOIntEna
IOControl
EFCR
DLL
DLH
EFR
XON1
XON2
XOFF1
XOFF2
MCR[7] can only be modified when EFR[4] is set.
Accessible only when ERF[4] = 1 and MCR[2] = 1, that is, EFR[4] and MCR[2] are read/write enables.
Available only on SC16IS750/SC16IS760.
Accessible only when LCR[7] is logic 1.
Accessible only when LCR is set to 1011 1111b (0xBF).
[3]
[3]
[3]
[3]
Register map - read/write properties
Receive Holding Register (RHR)
Interrupt Enable Register (IER)
Interrupt Identification Register (IIR)
Line Control Register (LCR)
Modem Control Register (MCR)
Line Status Register (LSR)
Modem Status Register (MSR)
Scratchpad Register (SPR)
Transmission Control Register (TCR)
Trigger Level Register (TLR)
Transmit FIFO Level Register
Receive FIFO Level Register
I/O pin Direction Register
I/O pin States Register
I/O Interrupt Enable Register
I/O pins Control Register
Extra Features Register
divisor latch LSB (DLL)
divisor latch MSB (DLH)
Enhanced Feature Register (EFR)
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Single UART with I
Rev. 06 — 13 May 2008
[5]
[5]
[5]
[5]
[4]
[4]
2
[2]
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
[1]
[5]
SC16IS740/750/760
[2]
Write mode
Transmit Holding Register (THR)
Interrupt Enable Register
FIFO Control Register (FCR)
Line Control Register
Modem Control Register
n/a
n/a
Scratchpad Register
Transmission Control Register
Trigger Level Register
n/a
n/a
I/O pin Direction Register
n/a
I/O Interrupt Enable Register
I/O pins Control Register
Extra Features Register
divisor latch LSB
divisor latch MSB
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
[5]
[5]
[5]
[5]
Table
© NXP B.V. 2008. All rights reserved.
[4]
[4]
9.
[2]
[1]
[5]
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[2]