SC16IS740IPW,112 NXP Semiconductors, SC16IS740IPW,112 Datasheet - Page 18
![IC UART SINGLE W/FIFO 16-TSSOP](/photos/6/56/65607/568-16-tssop_sot403-1_sml.jpg)
SC16IS740IPW,112
Manufacturer Part Number
SC16IS740IPW,112
Description
IC UART SINGLE W/FIFO 16-TSSOP
Manufacturer
NXP Semiconductors
Type
UART with 64-byte FIFOs and IrDA encoder/decoderr
Datasheet
1.SC16IS740IPW112.pdf
(62 pages)
Specifications of SC16IS740IPW,112
Number Of Channels
1, UART
Package / Case
16-TSSOP (0.173", 4.40mm Width)
Fifo's
64 Byte
Protocol
RS232, RS485
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
5 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.3 V
Supply Current
6 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.5 V, 3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-3648-5
935280988112
SC16IS740IPW
935280988112
SC16IS740IPW
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16IS740IPW,112
Manufacturer:
JAMICON
Quantity:
101
NXP Semiconductors
SC16IS740_750_760_6
Product data sheet
Figure 14
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the
least significant and most significant byte of the baud rate divisor. If DLL and DLH are both
zero, the UART is effectively disabled, as no baud clock will be generated.
Remark: The programmable baud rate generator is provided to select both the transmit
and receive clock rates.
Table 7
1.8432 MHz and 3.072 MHz, respectively.
Figure 15
Table 7.
Desired baud rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
Fig 14. Prescaler and baud rate generator block diagram
XTAL1
XTAL2
and
shows the internal prescaler and baud rate generator circuitry.
shows the crystal clock circuit reference.
Baud rates using a 1.8432 MHz crystal
Table 8
OSCILLATOR
INTERNAL
LOGIC
show the baud rate and divisor correlation for crystal with frequency
Single UART with I
Divisor used to generate
16 clock
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
Rev. 06 — 13 May 2008
input clock
(DIVIDE-BY-1)
(DIVIDE-BY-4)
PRESCALER
PRESCALER
LOGIC
LOGIC
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
SC16IS740/750/760
MCR[7] = 0
MCR[7] = 1
reference
clock
Percent error difference
between desired and actual
0
0
0.026
0.058
0
0
0
0
0
0.69
0
0
0
0
0
0
0
2.86
GENERATOR
BAUD RATE
LOGIC
© NXP B.V. 2008. All rights reserved.
002aaa233
internal
baud rate
clock for
transmitter
and receiver
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