PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 175
PEF 20525 F V1.3
Manufacturer Part Number
PEF 20525 F V1.3
Description
IC CTRL PPP/HDLC SERIAL TQFP-100
Manufacturer
Infineon Technologies
Datasheet
1.PEB_20525_F_V1.3.pdf
(252 pages)
Specifications of PEF 20525 F V1.3
Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Bit Processor Functions, Serial Communication Controllers (SCCs)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20525FV1.3X
PEF20525FV13XP
SP000007592
PEF20525FV13XP
SP000007592
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PEB 20525
PEF 20525
Register Description (PCMRX3)
PCMRX
PCM Mask for Receive Direction
This bit field is valid in clock mode 5 only and the PCM mask must be
enabled via bit ’REPCM’ in register RTSA1.
Each bit selects one of 32 (8-bit) receive time-slots. The offset of time-
slot zero to the frame sync pulse can be programmed via register
RTSA1
bit field ’RTSN’.
Data Sheet
5-175
2000-09-14
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