PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 140

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

Data Sheet
VIS
PSD
TOE
SSEL
Masked Interrupts Visible
VIS=’0’
VIS=’1’
Note: Interrupts masked in registers
DPLL Phase Shift Disable
This option is only applicable in the case of NRZ or NRZI line encoding
is selected.
PSD=’0’
PSD=’1’
Transmit Clock Out Enable
For clock modes 0b, 2b, 3a, 3b, 6b, 7a and 7b, the internal transmit clock
can be monitored on pin TxCLK as an output signal. In clock mode 5, a
time slot control signal marking the active transmit time slot is output on
pin TxCLK.
Bit ’TOE’ is invalid for all other clock modes.
TOE=’0’
TOE=’1’
Clock Source Select
Distinguishes between the ’a’ and ’b’ option of clock modes 0, 2, 3, 5, 6
and 7.
SSEL=’0’
SSEL=’1’
interrupt.
Masked interrupt status bits are not displayed in the
interrupt status registers (ISR0..ISR2).
Masked interrupt status bits are visible and automatically
cleared after interrupt status register (ISR0..ISR2) read
access.
Normal DPLL operation.
The phase shift function of the DPLL is disabled. The
windows for phase adjustment are extended.
TxCLK pin is input.
TxCLK pin is switched to output function if applicable for
the selected clock mode.
Option ’a’ is selected.
Option ’b’ is selected.
5-140
IMR0..IMR2
Register Description (CCR0H)
will not generate an
PEB 20525
PEF 20525
2000-09-14